# US 2017/0287536 A1 · Configuration Bit Sequencing Control of Nonvolatile Domain and Array Wakeup and Backup

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- Number: US 2017/0287536 A1
- Document ID: US20170287536A1
- Status: Published application
- Kind: A1
- Application number: 15/623,441
- Filed: 2017-06-15
- Published: 2017-10-05
- Earliest claimed: 2012-09-10
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Steven Craig Bartling; Sudhanshu Khanna
- Web page: https://patentgrep.com/patent/US20170287536A1

## CPC

- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode
- G06F 1/3234: Power saving characterised by the action undertaken
- G06F 1/3275: {Power saving in memory, e.g. RAM, cache}
- G06F 1/3287: by switching off individual functional units in the computer system
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 9/4401: Bootstrapping (security arrangements therefor G06F21/57)
- G06F 9/4406: {Loading of operating system}
- G06F 11/1032: {Simple parity}
- G06F 11/1438: {Restarting or rejuvenating}
- G06F 11/1469: {Backup restoration techniques}
- G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}
- G06F 13/00: Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor G06F9/46}; multiprocessor systems G06F15/16 )
- G11C 14/00: Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- H03K 3/3562: of the primary-secondary type
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- Y02D 30/50: in wire-line communication networks, e.g. low power modes or reduced link rate
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A processing device includes a plurality of non-volatile logic element array domains having two or more non-volatile logic element arrays to store 2006 a machine state of the processing device stored in a plurality of volatile store elements. Configuration bits are read to direct which non-volatile logic element array domains are enabled first and to direct an order in which the first enabled non-volatile logic element array domains are restored or backed up in response to entering a wakeup or backup mode. Configuration bits can be read to direct an order of and a parallelism of how individual non-volatile logic element arrays in a first enabled non-volatile logic element array domain are restored or backed up. The order of restoration or backing up can be controlled by instructions from non-volatile arrays of the first enabled of the plurality of non-volatile logic element array domains.

## Claims

### Claim 1

A computing device apparatus providing non-volatile logic based computing, the apparatus comprising:
a plurality of non-volatile logic element array domains wherein at least one of the non-volatile logic element array domains comprises two or more non-volatile logic element arrays;
a plurality of volatile storage elements;
at least one non-volatile logic controller configured to control the plurality of non-volatile logic element array domains to store a machine state represented by the plurality of volatile storage elements and to read out a stored machine state from the plurality of non-volatile logic element array domains to the plurality of volatile storage elements;
wherein the at least one non-volatile logic controller is further configured to read configuration bits that direct which of the plurality of non-volatile logic element array domains are enabled first in response to the computing device apparatus's entering a wakeup or backup mode;
wherein the at least one non-volatile logic controller is further configured to read configuration bits that direct an order in which the first enabled of the plurality of non-volatile logic element array domains are restored or backed up in response to the computing device apparatus's entering a wakeup or backup mode.

### Claim 2 (depends on 1)

The computing device apparatus of claim 1 wherein the at least one non-volatile logic controller is further configured to read configuration bits that direct whether and which individual ones of the two or more non-volatile logic element arrays in at least one of the first enabled of the plurality of non-volatile logic element array domains to restore or backup in parallel in response to the computing device apparatus's entering a wakeup or backup mode.

### Claim 3 (depends on 1)

The computing device apparatus of claim 1 wherein individual non-volatile arrays of the ones of the first enabled of the plurality of non-volatile logic element array domains include instructions for an order in which other non-volatile logic element arrays are to be restored next.

### Claim 4 (depends on 1)

The computing device apparatus of claim 1 wherein the at least one non-volatile logic controller is further configured to associate individual one or more functions with individual ones of the plurality of non-volatile logic element arrays.

### Claim 5 (depends on 1)

The computing device apparatus of claim 1 wherein the individual ones of the at least one function comprise any one of a plurality of peripheral functions for the computing device apparatus.

### Claim 6

A method comprising:
operating a processing device using a plurality of volatile storage elements to execute at least one function;
storing in a plurality of non-volatile logic element array domains, wherein at least one of the non-volatile logic element array domains comprises two or more non-volatile logic element arrays, a machine state of the processing device stored in the plurality of volatile store elements in response to the processing device entering a backup mode;
reading configuration bits to direct which of the plurality of non-volatile logic element array domains are enabled first in response to the processing device's entering a wakeup or backup mode;
reading configuration bits to direct an order in which the first enabled of the plurality of non-volatile logic element array domains are restored or backed up in response to the computing device apparatus's entering a wakeup or backup mode.

### Claim 7 (depends on 6)

The method of claim 6 further comprising reading configuration bits to direct an order of and whether and which individual ones of the two or more non-volatile logic element arrays in at least one of the first enabled of the plurality of non-volatile logic element array domains to restore or backup in parallel in response to the processing device's entering a wakeup or backup mode.

### Claim 8 (depends on 6)

The method of claim 6 further comprising associating individual ones of the at least one function with individual ones of the plurality of non-volatile logic element arrays.

### Claim 9 (depends on 8)

The method of claim 8 wherein the associating the at least one function with individual ones of the plurality of non-volatile logic element arrays further comprises designating any one of a plurality of peripheral functions for the processing device.