# US 2017/0287531 A1 · Apparatuses and methods for controlling data timing in a multi-memory system

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- Number: US 2017/0287531 A1
- Document ID: US20170287531A1
- Status: Published application
- Kind: A1
- Application number: 15/626,915
- Filed: 2017-06-19
- Published: 2017-10-05
- Earliest claimed: 2013-03-14
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Tsugio Takahashi; Zer Liang
- Web page: https://patentgrep.com/patent/US20170287531A1

## CPC

- G11C 7/1039: {using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers}
- G11C 7/1003: {Interface circuits for daisy chain or ring bus memory arrangements}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.

## Claims

### Claim 1

An apparatus comprising:
a first memory unit comprising a first memory control logic, a first memory and a first configurable delay circuit, the first memory control logic configured to receive a first read command and provide the first read command to the first memory, the first memory configured to receive the first read command and provide a first read data responsive to the first read command to a first output node;
a second memory unit comprising a second memory control logic, a second memory and a second configurable delay circuit, the second memory control logic configured to receive a second read command subsequently issued from the first read command and provide the second read command to the second memory, the second memory configured to receive the second read command and provide a second read data responsive to the second read command to a second output node; and
a through-silicon via (TSV) coupled to the first and second output nodes;
wherein the first configurable delay circuit is configured to exhibit a first delay value and the second configurable delay circuit is configured to exhibit a second delay value such that the first read data and the second read data do not collide with each on the TSV.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the first configurable delay circuit is configured to delay the first read command with the first delay value.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the second configurable delay circuit is configured to delay the second read command with the second delay value.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the second delay value is longer than the first delay value.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the first memory unit has a first timing characteristic and the second memory unit has a second timing characteristic different from the first timing characteristic.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the first and second memory units have the same architecture.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the first and second timing characteristics are based on variability in fabrication process.

### Claim 8 (depends on 1)

The apparatus of claim 1, further comprising:
a data pipeline coupled to the TSV.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the first memory is configured to output a first control signal to the data pipeline to direct the data pipeline to store the first read data.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the second memory is configured to output a second control signal to the data pipeline to direct the data pipeline to store the second read data.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein the first memory unit comprises a first fuse bank configured to indicate the first delay value.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the first memory unit comprises a second fuse bank configured to indicate the second delay value.

### Claim 13 (depends on 1)

The apparatus of claim 1, wherein the first memory unit comprises a control logic configured to receive the first and second read command and deliver the first read command to the first memory control logic and the second read command to the second memory control logic.

### Claim 14 (depends on 1)

The apparatus of claim 1, wherein the first configurable delay circuit is provided between the first memory control logic and the first memory.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the second configurable delay circuit is provided between the second memory control logic and the second memory.

### Claim 16 (depends on 1)

The apparatus of claim 1, wherein the first and second memory units are stacked to each other.

### Claim 17 (depends on 1)

The apparatus of claim 1, wherein the first memory unit comprises a timing characteristic measurement circuit to determine the first delay value.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein the timing characteristic measurement circuit is configured to determine the second delay value.

### Claim 19 (depends on 1)

The apparatus of claim 1, wherein the first configurable delay circuit is configured to receive a first column control signal corresponding to the first read command and the second configurable delay circuit is configured to receive a second column control signal corresponding to the second read command

### Claim 20 (depends on 19)

The apparatus of claim 19, wherein the first column control signal is delayed with the first delay value and the second column control signal is delayed with the second delay value.