# US 2017/0287435 A1 · Selectively transmitting signals > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0287435 A1 - Document ID: US20170287435A1 - Status: Published application - Kind: A1 - Application number: 15/087,561 - Filed: 2016-03-31 - Published: 2017-10-05 - Earliest claimed: 2016-03-31 - Assignees: Lenovo (Singapore) Pte. Ltd. - Applicants: LENOVO (Singapore) PTE. LTD. - Inventors: Marc Richard Pamley; Omar Ali Ali; George O. Diatzikis; Alan Ladd Painter - Web page: https://patentgrep.com/patent/US20170287435A1 ## CPC - G09G 5/006: {Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04)} - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G09G 5/363: {Graphics controllers} - G09G 2340/10: Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels - G09G 2350/00: Solving problems of bandwidth in display systems - G09G 2370/00: Aspects of data communication - G09G 2370/10: Use of a protocol of communication by packets in interfaces along the display data pipeline - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract For selectively transmitting signals, a data lane interface communicates signals of at least one data lane of a serial bus. A video interface port receives a video display signal from a video card. A traffic circuit transmits the signals of the at least one data lane and the video display signal to a high-speed signal combiner in response to determining that the high-speed signal combiner is processing the signals of the at least one data lane and the video display signal for output as a combined video display signal. Else the traffic circuit transmits the video display signal to a video output port in response to determining that the high-speed signal combiner is not processing the signals of the at least one data lane and the video display signal for output as the combined video display signal. ## Claims ### Claim 1 An apparatus comprising: a data lane interface that communicates signals of at least one data lane of a serial bus; a video interface port that receives a video display signal from a video card; and a traffic circuit that transmits the signals of the at least one data lane and the video display signal to a high-speed signal combiner in response to determining that the high-speed signal combiner is processing the signals of the at least one data lane and the video display signal for output as a combined video display signal, else the traffic circuit transmits the video display signal to a video output port in response to determining that the high-speed signal combiner is not processing the signals of the at least one data lane and the video display signal for output as the combined video display signal. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the traffic circuit determines that the high-speed signal combiner is processing the signals of the at least one data lane and the video display signal for output by detecting serial bus traffic on the at least one data lane. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the traffic circuit determines that the high-speed signal combiner is processing the signals of the at least one data lane and the video display signal for output from a configuration value. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the traffic circuit further conditions the signals of the at least one data lane and the video display signal, wherein the conditioned signals do not degrade prior to the reaching the high-speed signal combiner. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the serial bus is a Peripheral Component Interconnect Express 3 (PCIe-3) serial bus. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the video interface port is selected from the group consisting of a DisplayPort (DP) and a Mini DisplayPort (MDP). ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the combined video display signal and the signals of the at least one data lane conform to a standard selected from the group consisting of a THUNDERBOLT 1 standard, a THUNDERBOLT 2 standard, and a THUNDERBOLT 3 standard. ### Claim 8 A method comprising: communicating signals of at least one data lane of a serial bus through a data lane interface; receiving a video display signal from a video card through a video interface port; and transmitting the signals of the at least one data lane and the video display signal to a high-speed signal combiner in response to determining that the high-speed signal combiner is processing the signals of the at least one data lane and the video display signal for output as a combined video display signal, else transmitting the video display signal to a video output port in response to determining that the high-speed signal combiner is not processing the signals of the at least one data lane and the video display signal for output as the combined video display signal. ### Claim 9 (depends on 8) The method of claim 8, wherein the method determines that the high-speed signal combiner is processing the signals of the at least one data lane and the video display signal for output by detecting serial bus traffic on the at least one data lane. ### Claim 10 (depends on 8) The method of claim 8, wherein the method determines that the high-speed signal combiner is processing the signals of the at least one data lane and the video display signal for output from a configuration value. ### Claim 11 (depends on 8) The method of claim 8, wherein the method further conditions the signals of the at least one data lane and the video display signal, wherein the conditioned signals do not degrade prior to reaching the high-speed signal combiner. ### Claim 12 (depends on 8) The method of claim 8, wherein the serial bus is a Peripheral Component Interconnect Express 3 (PCIe-3) serial bus. ### Claim 13 (depends on 8) The method of claim 8, wherein the video interface port is selected from the group consisting of a DisplayPort (DP) and a Mini DisplayPort (MDP). ### Claim 14 (depends on 8) The method of claim 8, wherein the combined video display signal and the signals of the at least one data lane conform to a standard selected from the group consisting of a THUNDERBOLT 1 standard, a THUNDERBOLT 2 standard, and a THUNDERBOLT 3 standard. ### Claim 15 A system comprising: a motherboard; a high-speed signal combiner; a data lane interface that communicates signals of at least one data lane of a serial bus of the motherboard; a video interface port that receives a video display signal from a video card; and a traffic circuit that transmits the signals of the at least one data lane and the video display signal to the high-speed signal combiner in response to determining that the high-speed signal combiner is processing the signals of the at least one data lane and the video display signal for output as a combined video display signal, else the traffic circuit transmits the video display signal to a video output port in response to determining that the high-speed signal combiner is not processing the signals of the at least one data lane and the video display signal for output as the combined video display signal. ### Claim 16 (depends on 15) The system of claim 15, wherein the traffic circuit determines that the high-speed signal combiner is processing the signals of the at least one data lane and the video display signal for output by detecting serial bus traffic on the at least one data lane. ### Claim 17 (depends on 15) The system of claim 15, wherein the traffic circuit determines that the high-speed signal combiner is processing the signals of the at least one data lane and the video display signal for output from a configuration value. ### Claim 18 (depends on 15) The system of claim 15, wherein the traffic circuit further conditions the signals of the at least one data lane and the video display signal, wherein the conditioned signals do not degrade prior to reaching the high-speed signal combiner. ### Claim 19 (depends on 15) The system of claim 15, wherein the traffic circuit further transmits the signals of the at least one data lane and the video display signal to the high-speed signal combiner and mirrors the video display signal to the video output port in response to determining that the high-speed signal combiner is processing the signals of the at least one data lane and the video display signal for output as a combined video display signal and determining that a video device is connected to the video output port ### Claim 20 (depends on 15) The system of claim 15, wherein the traffic circuit further transmits the signals of the at least one data lane and the video display signal to the high-speed signal combiner and mirrors the video display signal to the video output port in response to determining that the high-speed signal combiner is processing the signals of the at least one data lane and the video display signal for output as a combined video display signal and a mirror video value is asserted.