# US 2017/0287434 A1 · Display apparatus, control method, and semiconductor apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0287434 A1 - Document ID: US20170287434A1 - Status: Published application - Kind: A1 - Application number: 15/471,530 - Filed: 2017-03-28 - Published: 2017-10-05 - Earliest claimed: 2016-03-30 - Assignees: Japan Display Inc. - Applicants: Japan Display Inc. - Inventors: Tamotsu Uekuri - Web page: https://patentgrep.com/patent/US20170287434A1 ## CPC - G09G 5/003: {Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto (specific for a CRT G09G1/165; for a flat panel G09G3/2092)} - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/60: wherein the TFTs are in active matrices - G09G 2300/0452: Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components - G09G 2310/0218: with collection of electrodes in groups for n-dimensional addressing - G09G 2310/027: Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters - G09G 2310/0297: Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/0209: Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display - G09G 2330/026: Arrangements or methods related to booting a display - G09G 2330/027: Arrangements or methods related to powering off a display - G09G 2370/08: Details of image data interface between the display device controller and the data line driver circuit - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract According to an aspect, a display apparatus includes: a plurality of pixels formed on a substrate; a plurality of semiconductor apparatuses, each of which is coupled to a part of the pixels, the part being different for each semiconductor apparatus; and wiring that couples the semiconductor apparatuses to one another. Each semiconductor apparatus includes a drive signal output circuit configured to output a drive signal to the part of the pixels, and an output controller configured to: output and receive, to and from other semiconductor apparatuses, a drive communication signal including a drive start communication signal indicating reception of a drive start signal to start driving the pixels via the wiring; and cause the drive signal output circuit to output the drive signal when determining that all the semiconductor apparatuses have received the drive start signals in accordance with the drive start communication signal. ## Claims ### Claim 1 A display apparatus comprising: a plurality of pixels formed on a substrate; a plurality of semiconductor apparatuses, each of which is coupled to a part of the pixels, the part being different for each semiconductor apparatus; and wiring that couples the semiconductor apparatuses to one another, wherein each semiconductor apparatus includes a drive signal output circuit configured to output a drive signal to the part of the pixels, and an output controller configured to: output and receive, to and from other semiconductor apparatuses, a drive communication signal including a drive start communication signal indicating reception of a drive start signal to start driving the pixels via the wiring; and cause the drive signal output circuit to output the drive signal when determining that all the semiconductor apparatuses have received the drive start signals in accordance with the drive start communication signal. ### Claim 2 (depends on 1) The display apparatus according to claim 1, wherein each semiconductor apparatus includes an external input interface configured to individually receive the drive start signal. ### Claim 3 (depends on 1) The display apparatus according to claim 1, wherein the wiring includes first wiring, the semiconductor apparatuses include a first semiconductor apparatus and a second semiconductor apparatus coupled to the first semiconductor apparatus via the first wiring, each of the first semiconductor apparatus and the second semiconductor apparatus includes an external input interface configured to receive the drive start signal, the output controller of the first semiconductor apparatus includes a first determination circuit, and the first determination circuit is configured to determine whether the first semiconductor apparatus and the second semiconductor apparatus have received the drive start signal in accordance with the drive start signal received via the external interface of the first semiconductor apparatus and the drive start communication signal received from the second semiconductor apparatus via the first wiring. ### Claim 4 (depends on 3) The display apparatus according to claim 3, wherein the second semiconductor apparatus is located at an end of the semiconductor apparatuses coupled to one another via the wiring, and the output controller of the second semiconductor apparatus is configured to output the drive start communication signal to the first semiconductor apparatus when receiving the drive start signal. ### Claim 5 (depends on 3) The display apparatus according to claim 3, wherein the wiring includes second wiring, the semiconductor apparatuses further include a third semiconductor apparatus coupled to the first semiconductor apparatus via the second wiring, the output controller of the first semiconductor apparatus includes a second determination circuit, the second determination circuit is configured to determine the first semiconductor apparatus and the third semiconductor apparatus have received the drive start signal in accordance with a first determination signal indicating a result of the determination made by the first determination circuit and the drive start communication signal received from the third semiconductor apparatus via the second wiring, and the drive signal output circuit of the first semiconductor apparatus is configured to start outputting the drive signal in accordance with a second determination signal indicating a result of the determination made by the second determination circuit. ### Claim 6 (depends on 5) The display apparatus according to claim 5, wherein the first semiconductor apparatus is coupled to the third semiconductor apparatus via the first wiring, and the output controller of the first semiconductor apparatus is configured to output the drive start communication signal to the third semiconductor apparatus in accordance with the first determination signal. ### Claim 7 (depends on 5) The display apparatus according to claim 5, wherein the third semiconductor apparatus is located at the other end of the semiconductor apparatuses coupled to one another via the wiring, and the output controller of the third semiconductor apparatus is configured to: cause the drive signal output circuit to output the drive signal when receiving the drive start communication signal from the first semiconductor apparatus and the drive start signal via the external input interface; and output the drive communication signal to the first semiconductor apparatus via the second wiring. ### Claim 8 (depends on 5) The display apparatus according to claim 5, wherein the first semiconductor apparatus is coupled to the second semiconductor via the second wiring, and the output controller of the first semiconductor apparatus is configured to output the drive start communication signal to the second semiconductor apparatus via the second wiring in accordance with the second determination signal. ### Claim 9 (depends on 1) The display apparatus according to claim 1, wherein the output controller of a first end semiconductor apparatus located at an end of the semiconductor apparatuses coupled via the wiring is configured to output, when receiving the drive start signal, a first drive start communication signal indicating reception of the drive start signal to another semiconductor apparatus coupled to the first end semiconductor apparatus, the output controller of an intermediate semiconductor apparatus that is not located at either end of the semiconductor apparatuses coupled via the wiring is configured to output, when receiving the first drive start communication signal from another semiconductor apparatus coupled to the intermediate semiconductor apparatus and receiving the drive start signal, the first drive start communication signal to still another semiconductor apparatus coupled to the intermediate semiconductor apparatus, the output controller of a second end semiconductor apparatus located at the other end of the semiconductor apparatuses coupled via the wiring, the output controller is configured to, when receiving the drive start communication signal from another semiconductor apparatus coupled to the second end semiconductor apparatus and receiving the drive start signal, cause the drive signal output circuit to start outputting the drive signal and output a second drive start communication signal indicating that all the semiconductor apparatuses have received the drive start signal to the another semiconductor apparatus coupled to the second end semiconductor apparatus, the output controller of the intermediate semiconductor apparatus is configured to, when receiving the second drive start communication signal from another semiconductor apparatus coupled to the intermediate semiconductor apparatus, cause the drive signal output circuit to start outputting the drive signal and output the second drive start communication signal to still another semiconductor apparatus coupled to the intermediate semiconductor apparatus, and the output controller of the first end semiconductor apparatus is configured to cause, when receiving the second drive start communication signal from another semiconductor apparatus coupled to the first end semiconductor apparatus, the drive signal output circuit to start outputting the drive signal. ### Claim 10 (depends on 1) The display apparatus according to claim 1, wherein the output controller is configured to output and receive, to and from other semiconductor apparatuses, the drive communication signal including a drive stop communication signal indicating reception of a drive stop signal to stop driving the pixels, and, when determining that any one of the semiconductor apparatuses has received the drive stop signal in accordance with the drive stop communication signal, cause the drive signal output circuit to stop outputting the drive signal. ### Claim 11 (depends on 10) The display apparatus according to claim 10, wherein when the output controller of one semiconductor apparatus included in the semiconductor apparatuses receives the drive stop signal, the output controller is configured to cause the drive signal output circuit to stop outputting the drive signal, and output the drive stop communication signal to another semiconductor apparatus coupled to the one semiconductor apparatus, and when the output controller of the one semiconductor receives the drive stop communication signal from another semiconductor apparatus coupled to the one semiconductor apparatus, the output controller is configured to cause the drive signal output circuit to stop outputting the drive signal, and output, to still another semiconductor apparatus coupled to the one semiconductor apparatus, the drive stop communication signal. ### Claim 12 (depends on 1) The display apparatus according to claim 1, wherein each semiconductor apparatus includes a plurality of terminals configured to output and receive the drive communication signal to and from other semiconductor apparatuses. ### Claim 13 (depends on 1) The display apparatus according to claim 1, wherein each semiconductor apparatus includes a plurality of terminals configured to output and receive the drive communication signal to and from other semiconductor apparatuses and output and receive a signal for adjusting an image displayed by the pixels to and from the other semiconductor apparatuses. ### Claim 14 (depends on 1) The display apparatus according to claim 1, wherein the output controller of one semiconductor apparatus included in the semiconductor apparatuses includes a logical AND operation circuit, and the logical AND operation circuit is configured to perform a logical AND operation in accordance with the drive start signal received by the one semiconductor apparatus and the drive start signal received by the other semiconductor apparatus, and output a result of the logical AND operation to the drive signal output circuit. ### Claim 15 (depends on 1) The display apparatus according to claim 1, wherein the output controller of one semiconductor apparatus included in the semiconductor apparatuses includes a first logical AND operation circuit including a first input terminal to which the drive start signal received by the one semiconductor apparatus is input and a second input terminal to which the drive communication signal received from another semiconductor apparatus coupled to the one semiconductor apparatus is input, the first logical AND operation circuit configured to perform a logical AND operation in accordance with the signals input to the first and second input terminals, and a second logical AND operation circuit including a first input terminal to which the drive communication signal received from still another semiconductor apparatus coupled to the one semiconductor apparatus is input, a second input terminal to which the drive start signal received by the one semiconductor apparatus is input, and a third input terminal to which an output signal from the first logical AND operation circuit is input, the second logical AND operation circuit configured to perform a logical AND operation in accordance with the signals input to the first, second, and third input terminals, and output a result of the logical AND operation to the drive signal output circuit. ### Claim 16 (depends on 15) The display apparatus according to claim 15, wherein the output controller includes a first switch circuit configured to input either of the drive communication signal received from another semiconductor apparatus coupled to the one semiconductor apparatus or a power supply potential at a higher voltage level to the second input terminal of the first logical AND operation circuit, and a second switch circuit configured to input either of the drive communication signal received from still another semiconductor apparatus coupled to the one semiconductor apparatus or the power supply potential at the higher voltage level to the first input terminal of the second logical AND operation circuit. ### Claim 17 (depends on 15) The display apparatus according to claim 15, wherein the output controller includes a status register a value of which is readable from outside, and the drive start signal or a drive stop signal to stop driving the pixels received by the output controller and an output signal from the second logical AND operation circuit are set to the status register. ### Claim 18 (depends on 16) The display apparatus according to claim 16, wherein the output controller includes a setting register a value of which is writable from outside, the setting register is configured to control the first switch circuit to input the power supply potential at the higher voltage level to the second input terminal of the first logical AND operation circuit when the one semiconductor apparatus is located at an end of the semiconductor apparatuses coupled via the wiring, and the setting register is configured to control the second switch circuit to input the power supply potential at the higher voltage level to the first input terminal of the second logical AND operation circuit when the one semiconductor apparatus located at the other end of the semiconductor apparatuses coupled via the wiring. ### Claim 19 A control method performed by a plurality of semiconductor apparatuses, each of which is coupled to a part of a plurality of pixels, the part being different for each semiconductor apparatus, the control method comprising: outputting and receiving, to and from other semiconductor apparatuses, a drive communication signal including a drive start communication signal indicating reception of a drive start signal to start driving the pixels; determining whether all the semiconductor apparatuses have received the drive start signal in accordance with the drive start communication signal; and starting output of the drive signal. ### Claim 20 A semiconductor apparatus comprising: a drive signal output circuit configured to output a drive signal; an output controller configured to control the drive signal output circuit; and an external input interface configured to receive a drive start signal, wherein the output controller is configured to output and receive, to and from other semiconductor apparatuses, a drive communication signal including a drive start communication signal indicating reception of the drive start signal, and the output controller is configured to cause the drive signal output circuit to output the drive signal when receiving the drive start communication signal and the drive start signal.