# US 2017/0287432 A1 · Display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0287432 A1 - Document ID: US20170287432A1 - Status: Published application - Kind: A1 - Application number: 15/470,968 - Filed: 2017-03-28 - Published: 2017-10-05 - Earliest claimed: 2016-03-29 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: JIHEE YOON; Kang-woo Kim; Beomjun Kim; Jonghwan Lee; Hong-woo Lee - Web page: https://patentgrep.com/patent/US20170287432A1 ## CPC - G09G 3/3696: {Generation of voltages supplied to electrode drivers} - G09G 3/2074: {using sub-pixels} - G09G 3/3614: {Control of polarity reversal in general} - G09G 3/3659: {the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes} - G09G 3/3677: {suitable for active matrices only} - G09G 3/3688: {suitable for active matrices only} - G09G 2300/0852: being a dynamic memory with more than one capacitor - G09G 2310/0205: Simultaneous scanning of several lines in flat panels - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A display device includes a display panel having a plurality of pixels respectively connected to a plurality of gate lines and a plurality of data lines, a gate driving circuit that outputs a plurality of gate signals to the plurality of gate lines, and a data driving circuit configured that outputs a plurality of data signals for driving the plurality of data lines. Each of the plurality of pixels includes a first sub-pixel configured to receive a corresponding data signal among the plurality of data signals in response to a first gate signal among the plurality of gate signals, and a second sub-pixel configured to receive a corresponding data signal among the plurality of data signals in response to the first gate signal, and reduce a voltage of the received data signal in response to a second gate signal among the plurality of gate signals. The second gate signal is a signal delayed by a 2×d×H time relative to the first gate signal (where each of d and H is a positive integer, H is a horizontal period, and d×H is a pulse width of first and second gate signals). ## Claims ### Claim 1 A display device comprising: a display panel comprising a plurality of pixels respectively connected to a plurality of gate lines and a plurality of data lines; a gate driving circuit configured to generate a plurality of gate signals to the plurality of gate lines; and a data driving circuit configured to generate a plurality of data signals to drive the plurality of data lines, wherein each of the plurality of pixels comprises at least two sub-pixels in which a first sub-pixel is configured to receive a corresponding data signal among the plurality of data signals in response to a first gate signal output by the gate driving circuit, and a second sub-pixel is configured to receive a corresponding data signal among the plurality of data signals in response to the first gate signal, and reduce a voltage of the received data signal in response to a second gate signal output by the gate driving circuit, wherein the second gate signal is delayed by a 2×d×H time relative to the first gate signal, where d and H are positive integers, H is a horizontal period, and d×H is a pulse width of the first gate signal and the second gate signal. ### Claim 2 (depends on 1) The display device of claim 1, wherein when a pulse width of the first gate signal and the second gate signal is 2×H, if the first gate signal comprises an i-th gate signal among the plurality of gate signals, the second gate signal comprises an (i+4)th gate signal. ### Claim 3 (depends on 1) The display device of claim 1, wherein the first sub-pixel comprises: a first switching transistor comprising a first electrode connected to a corresponding data line driven by the data driving circuit, a second electrode connected to a first node, and a gate electrode connected to a corresponding first gate line driven by the gate driving circuit; a first liquid crystal capacitor connected between the first node and a first common electrode for receiving a common voltage; and a first storage capacitor connected between the first node and a storage electrode for receiving a storage voltage. ### Claim 4 (depends on 1) The display device of claim 1, wherein the second sub-pixel comprises: a second switching transistor comprising a first electrode connected to a corresponding data line driven by the data driving circuit, a second electrode connected to a second node, and a gate electrode connected to a corresponding first gate line driven by the gate driving circuit; a second liquid crystal capacitor connected between the second node and a second common electrode for receiving a common voltage; a second storage capacitor connected between the second node and a storage electrode for receiving a storage voltage; a third switching transistor comprising a first node connected to the second node, a second electrode connected to a third node, and a gate electrode connected to a second gate line driven by the gate driving circuit; and a pull-down capacitor connected between the third node and the storage electrode to reduce a voltage of the second node. ### Claim 5 (depends on 4) The display device of claim 4, wherein when a pulse width of the first gate signal and the second gate signal is 2×H, if the first gate line is an i-th gate line among the plurality of gate lines, the second gate line is an (i+4)th gate line. ### Claim 6 (depends on 4) The display device of claim 4, wherein when a pulse width of the first gate signal and the second gate signal is 4×H, if the first gate line is an i-th gate line among the plurality of gate lines, the second gate line is an (i+8)th gate line. ### Claim 7 (depends on 1) The display device of claim 1, further comprising a driving controller that outputs control signals to the gate driving circuit and the data driving circuit based on received image data. ### Claim 8 (depends on 7) The display device of claim 7, wherein the driving controller receives image data and corresponding command signals from an external graphic control unit. ### Claim 9 A display device comprising: a display panel comprising a plurality of pixels respectively connected to a plurality of gate lines and a plurality of data lines; a gate driving circuit configured to generate a plurality of gate signals output to the plurality of gate lines and outputs a plurality of carry signals corresponding to the plurality of gate signals; and a data driving circuit configured to generate a plurality of data signals for driving the plurality of data lines, wherein each of the plurality of pixels comprises: a first sub-pixel configured to receive a corresponding data signal among the plurality of data signals in response to a corresponding first gate signal among the plurality of gate signals; and a second sub-pixel configured to receive a corresponding data signal among the plurality of data signals in response to the first gate signal, and reduce a voltage of the received data signal in response to a first carry signal corresponding to the first gate signal among the plurality of carry signals. ### Claim 10 (depends on 9) The display device of claim 9, wherein the first carry signal corresponds to a gate signal delayed by a d×H+1 time relative to the first gate signal, where d and H are positive integers, H is a horizontal period, and d×H is a pulse width of a gate signal. ### Claim 11 (depends on 9) The display device of claim 9, wherein when a pulse width of the first gate signal is 2H in which H is a horizontal period) if the first gate signal is an i-th gate signal among the plurality of gate signals, the first carry signal is an (i+3)th carry signal among the plurality of carry signals. ### Claim 12 (depends on 9) The display device of claim 9, wherein the first sub-pixel comprises: a first switching transistor comprising a first electrode connected to a corresponding data line among the plurality of data lines, a second electrode connected to a first node, and a gate electrode connected to a corresponding first gate line among the plurality of gate lines; a first liquid crystal capacitor connected between the first node and a common electrode for receiving a common voltage. ### Claim 13 (depends on 12) The display device of claim 12, further comprising a first storage capacitor connected between the first node and a storage electrode for receiving a storage voltage. ### Claim 14 (depends on 9) The display device of claim 9, wherein the second sub-pixel comprises: a second switching transistor comprising a first electrode connected to a corresponding data line among the plurality of data lines, a second electrode connected to a second node, and a gate electrode connected to a corresponding first gate line among the plurality of gate lines; a second liquid crystal capacitor connected between the second node and a common electrode for receiving a common voltage; a third switching transistor comprising a first node connected to the second node, a second electrode connected to a third node, and a gate electrode for receiving a first carry signal among the plurality of carry signals; and a pull-down capacitor connected between the third node and the storage electrode. ### Claim 15 (depends on 14) The display device of claim 14, further comprising a second storage capacitor connected between the second node and the storage electrode. ### Claim 16 (depends on 9) The display device of claim 9, wherein the gate driving circuit includes a plurality of driving stages in a cascaded arrangement in which one or more driving stages operates in response to a received carry signal outputted from a previous stage and a carry signal outputted from the next stage in the cascaded arrangement. ### Claim 17 A display panel comprising: a display panel comprising a plurality of pixels respectively connected to a plurality of gate lines to output respective gate signals and a plurality of data lines to output respective data signals, and in which each pixel is comprised of at least a first sub-pixel and a second sub-pixel that face each other with a first gate line arranged therebetween; the first sub-pixel is configured to receive a corresponding data signal among a plurality of data signals in response to a first gate signal through the first gate line, and the second sub-pixel configured to receive a corresponding data signal among the plurality of data signals in response to the first gate signal, and reduce a voltage of the received data signal in response to a second gate signal received through a second gate line. ### Claim 18 (depends on 17) The display panel of claim 17, wherein the first sub-pixel comprises: a first switching transistor comprising a first electrode connected to a corresponding data line among the plurality of data lines, a second electrode connected to a first node, and a gate electrode connected to the first gate line; a first liquid crystal capacitor connected between the first node and a common electrode for receiving a common voltage. ### Claim 19 (depends on 18) The display panel of claim 18, wherein the second sub-pixel comprises: a second switching transistor comprising a first electrode connected to a corresponding data line driven by a data driving circuit, a second electrode connected to a second node, and a gate electrode connected to the first gate line driven by a gate driving circuit; a second liquid crystal capacitor connected between the second node and a second common electrode for receiving a common voltage; a second storage capacitor connected between the second node and a storage electrode for receiving a storage voltage; a third switching transistor comprising a first node connected to the second node, a second electrode connected to a third node, and a gate electrode connected to the second gate line driven by the gate driving circuit; and a pull-down capacitor connected between the third node and the storage electrode to reduce a voltage of the second node.