# US 2017/0287404 A1 · Scan driver and related display apparatus

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- Number: US 2017/0287404 A1
- Document ID: US20170287404A1
- Status: Published application
- Kind: A1
- Application number: 15/458,668
- Filed: 2017-03-14
- Published: 2017-10-05
- Earliest claimed: 2016-03-31
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., LTD.
- Inventors: Ji-Hye KIM; Min-Kyu WOO
- Web page: https://patentgrep.com/patent/US20170287404A1

## CPC

- G09G 3/3266: Details of drivers for scan electrodes
- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- G09G 3/3291: in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- G09G 2300/0426: Layout of electrodes and connections
- G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
- G09G 2300/0871: with level shifting
- G09G 2310/0278: Details of driving circuits arranged to drive both scan and data electrodes
- G09G 2310/0283: Arrangement of drivers for different directions of scanning
- G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit
- G09G 2310/0291: Details of output amplifiers or buffers arranged for use in a driving circuit
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A scan driver may include a first stage, a second stage, and a third stage. The first stage may include a first output transistor. The first output transistor may have a first buffer value. The second stage may be electrically connected to the first output transistor and may include a second output transistor. The second output transistor may have a second buffer value. The third stage may be electrically connected to the second output transistor and may include a third output transistor. The third output transistor may have a third buffer value. At least one of the second buffer value and the third buffer value may be unequal to the first buffer value.

## Claims

### Claim 1

A scan driver comprising a plurality of stages, the plurality of stages outputting scan writing signals through a plurality of scan lines, the plurality of stages being sequentially disposed,
wherein each of the stages comprises a signal output part configured to output the scan writing signal to a corresponding scan line,
wherein a buffer size of the signal output part of an x-th stage of the stages is unequal to a buffer size of the signal output part of a y-th stage of the stages,
wherein x is a natural number, and
wherein y is another natural number.

### Claim 2 (depends on 1)

The scan driver of claim 1, wherein each of the stages is configured to output at least two scan writing pulses to a corresponding scan line during a frame.

### Claim 3 (depends on 2)

The scan driver of claim 2, wherein when each of the stages is configured to output three scan writing pulses to a corresponding scan line during a frame and an n-th stage is a last stage of the stages,
a buffer size of a first output transistor of the signal output part of the n-th stage is less than a buffer size of a first output transistor of the signal output part of an (n−2)-th stage, and
the buffer size of the first output transistor of the signal output part of the (n−2)-th stage is less than a buffer size of a first output transistor of the signal output part of an (n−4)-th stage,
wherein n is a natural number.

### Claim 4 (depends on 3)

The scan driver of claim 3, wherein when each of the stages is configured to output three scan writing pulses to a corresponding scan line during a frame and the n-th stage is the last stage of the stages,
the buffer size of the first output transistor of the signal output part of the n-th stage is substantially equal to a buffer size of a first output transistor of the signal output part of an (n−1)-th stage, and
the buffer size of the first output transistor of the signal output part of the (n−2)-th stage is substantially equal to a buffer size of a first output transistor of the signal output part of an (n−3)-th stage.

### Claim 5 (depends on 2)

The scan driver of claim 2, wherein when each of the stages is configured to output four scan writing pulses to a corresponding scan line during a frame and an n-th stage is a last stage of the stages,
a buffer size of a first output transistor of the signal output part of the n-th stage is less than a buffer size of a first output transistor of the signal output part of an (n−2)-th stage,
the buffer size of the first output transistor of the signal output part of the (n−2)-th stage is less than a buffer size of a first output transistor of the signal output part of an (n−4)-th stage, and
the buffer size of the first output transistor of the signal output part of the (n−4)-th stage is less than a buffer size of a first output transistor of the signal output part of an (n−6)-th stage,
wherein n is a natural number.

### Claim 6 (depends on 5)

The scan driver of claim 5, wherein when each of the stages is configured to output four scan writing pulses to a corresponding scan line during a frame and the n-th stage is the last stage of the stages,
the buffer size of the first output transistor of the signal output part of the n-th stage is substantially equal to as a buffer size of a first output transistor of the signal output part of an (n−1)-th stage,
the buffer size of the first output transistor of the signal output part of the (n−2)-th stage is substantially equal to a buffer size of a first output transistor of the signal output part of an (n−3)-th stage, and
the buffer size of the first output transistor of the signal output part of the (n−4)-th stage is substantially equal to a buffer size of a first output transistor of the signal output part of an (n−5)-th stage.

### Claim 7 (depends on 2)

The scan driver of claim 2, wherein when each of the stages is configured to output two scan writing pulses to a corresponding scan line during a frame and an n-th stage is a last stage of the stages,
a buffer size of a first output transistor of the signal output part of the n-th stage is less than a buffer size of a first output transistor of the signal output part of an (n−2)-th stage,
wherein n is a natural number.

### Claim 8 (depends on 7)

The scan driver of claim 7, wherein when each of the stages is configured to output two scan writing pulses to a corresponding scan line during a frame and the n-th stage is the last stage of the stages,
the buffer size of the first output transistor of the signal output part of the n-th stage is substantially equal to a buffer size of a first output transistor of the signal output part of an (n−1)-th stage.

### Claim 9 (depends on 1)

The scan driver of claim 1, wherein each of the stages further comprises:
a pulse detecting part configured to detect a pulse of an input signal to activate a pull down control node in response to a first clock signal;
a pull down control part configured to initialize the pull down control node in response to a second clock signal; and
a pull up control part configured to adjust a signal of a pull up control node in response to the first clock signal and a signal of the pull down control node, and
wherein the signal output part is configured to output the scan writing signal in response to the signal of the pull down control node and the signal of the pull up control node,
wherein the signal output part comprises:
a pull down part configured to generate a scan writing pulse of the scan writing signal in response to the signal of the pull down control node; and
a pull up part configured to maintain a high level of the scan writing signal in response to the signal of the pull up control node.

### Claim 10 (depends on 9)

The scan driver of claim 9, wherein a buffer size of a transistor of the pull down part of the x-th stage is unequal to a buffer size of a transistor of the pull down part of the y-th stage.

### Claim 11 (depends on 9)

The scan driver of claim 9, wherein a buffer size of a transistor of the pull down part of the x-th stage is unequal to a buffer size of a transistor of the pull down part of the y-th stage, and
wherein a buffer size of a transistor of the pull up part of the x-th stage is unequal to a buffer size of a transistor of the pull up part of the y-th stage.

### Claim 12 (depends on 9)

The scan driver of claim 9, wherein the pulse detecting part comprises a first transistor, the first transistor comprising a gate electrode to which the first clock signal is applied, a source electrode to which the input signal is applied and a drain electrode connected to a first node,
wherein the pull down control part comprises a second transistor and a third transistor, the second transistor comprising a gate electrode connected to the pull up control node, a source electrode to which a first power voltage is applied and a drain electrode connected to a source electrode of the third transistor, the third transistor comprising a gate electrode to which the second clock signal is applied, the source electrode connected to the drain electrode of the second transistor and a drain electrode connected to the first node,
wherein the pull up control part comprises a fourth transistor and a fifth transistor, the fourth transistor comprising a gate electrode connected to the first node, a source electrode connected to the gate electrode of the second transistor and a drain electrode connected to a second node, the fifth transistor comprising a gate electrode connected to the second node, a source electrode connected to the gate electrode of the second transistor and a drain electrode to which a second power voltage is applied,
wherein the pull down part comprises the first output transistor, the first output transistor comprising a gate electrode connected to the pull down control node, a source electrode connected to an output node and a drain electrode to which the second clock signal is applied, and
wherein the pull up part comprises a second output transistor, the second output transistor comprising a gate electrode connected to the gate electrode of the second transistor, a source electrode to which the first power voltage is applied and a drain electrode connected to the output node.

### Claim 13 (depends on 1)

The scan driver of claim 1, wherein each of the stages comprises a scan writing stage configured to output the scan writing signal, a scan initialization stage configured to output a scan initialization signal and a scan bypass stage configured to output a scan bypass signal.

### Claim 14 (depends on 1)

The scan driver of claim 1, wherein the buffer size of the first output transistor is a width-to-length ratio of the first output transistor.

### Claim 15

A display apparatus comprising:
a display panel comprising a plurality of scan lines, a plurality of data lines and a plurality of pixels connected to the plurality of scan lines and the plurality of data lines;
a scan driver comprising a plurality of stages, the plurality of stages being connected to the plurality of pixels through the plurality of scan lines, the plurality of stages being sequentially disposed; and
a data driver configured to provide data voltages to the plurality of data lines,
wherein each of the stages comprises a signal output part configured to output a scan writing signal to a corresponding scan line,
wherein a buffer size of the signal output part of an x-th stage of the stages is unequal to a buffer size of the signal output part of a y-th stage of the stages,
wherein x is a natural number, and
wherein y is another natural number.

### Claim 16 (depends on 15)

The display apparatus of claim 15, wherein each of the stages is configured to output at least two scan writing pulses to a corresponding scan line during a frame.

### Claim 17 (depends on 15)

The display apparatus of claim 15, wherein each of the stages further comprises:
a pulse detecting part configured to detect a pulse of an input signal to activate a pull down control node in response to a first clock signal;
a pull down control part configured to initialize the pull down control node in response to a second clock signal; and
a pull up control part configured to adjust a signal of a pull up control node in response to the first clock signal and a signal of the pull down control node, and
wherein the signal output part is configured to output the scan writing signal in response to the signal of the pull down control node and the signal of the pull up control node.

### Claim 18 (depends on 17)

The display apparatus of claim 17, wherein the signal output part comprises:
a pull down part configured to generate a scan writing pulse of the scan writing signal in response to the signal of the pull down control node; and
a pull up part configured to maintain a high level of the scan writing signal in response to the signal of the pull up control node.

### Claim 19 (depends on 18)

The display apparatus of claim 18, wherein a buffer size of a transistor of the pull down part of the x-th stage is unequal to a buffer size of a transistor of the pull down part of the y-th stage.

### Claim 20

A scan driver comprising:
a first stage comprising a first output part, the first output part comprising a first output transistor and configured to provide a first signal, the first output transistor having a first buffer value;
a second stage electrically connected to the first output transistor, configured to receive a copy of the first signal, and comprising a second output part, the second output part comprising a second output transistor and configured to provide a second signal, the second output transistor having a second buffer value; and
a third stage electrically connected to the second output transistor, configured to receive a copy of the second signal, and comprising a third output part, the third output part comprising a third output transistor and configured to provide a third signal, the third output transistor having a third buffer value, at least one of the second buffer value and the third buffer value being unequal to the first buffer value.