# US 2017/0287207 A1 · Apparatus and method for conservative rasterization of polygons > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0287207 A1 - Document ID: US20170287207A1 - Status: Published application - Kind: A1 - Application number: 15/089,168 - Filed: 2016-04-01 - Published: 2017-10-05 - Earliest claimed: 2016-04-01 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: FRANZ PETRIK CLARBERG - Web page: https://patentgrep.com/patent/US20170287207A1 ## CPC - G06T 15/30: Clipping - G06T 11/40: Filling planar surfaces by adding surface attributes, e.g. adding colours or textures - G06T 15/005: {General purpose rendering architectures} - G06T 15/40: Hidden part removal - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ## Abstract An apparatus and method are described for conservative rasterization. For example, one embodiment of a graphics processing apparatus comprises: an edge tagging circuit to identify edges of two or more triangles forming a convex polygon as inner edges or non-inner edges; and a rasterizer to responsively perform rasterization of the two or more triangles using a first edge processing circuit for inner edges and a second edge processing circuit for non-inner edges. ## Claims ### Claim 1 A graphics processing apparatus comprising: an edge tagging circuit to identify edges of two or more triangles forming a convex polygon as inner edges or non-inner edges; and a rasterizer to responsively perform rasterization of the two or more triangles using a first edge processing circuit that comprises logic and/or circuitry to implement a first edge test applied to center points of pixels overlapping inner edges and a second edge processing circuit that comprises logic and/or circuitry to implement a second edge test applied to corner points of pixels overlapping non-inner edges. ### Claim 2 (depends on 1) The graphics processing apparatus as in claim 1 wherein the second edge test is applied the corner points nearest the non-inner edges for an overestimating edge test or the second edge test is applied to the corner points farthest from the non-inner edges for an underestimating edge test. ### Claim 3 (depends on 2) The graphics processing apparatus as in claim 2 further comprising: a clipping or setup circuit to perform clipping or setup operations for the rasterizer, the edge tagging circuit to be integrated within the clipping or setup circuit. ### Claim 4 (depends on 3) The graphics processing apparatus as in claim 3 wherein the two or more triangles comprise a first triangle and a second triangle sharing an inner edge and wherein the first edge test implemented for the first and second triangles ensures that no pixels overlapping the inner edge are generated multiple times. ### Claim 5 (depends on 4) The graphics processing apparatus as in claim 4 wherein the clipping circuit clips the first and second triangles against a view frustum, guard bands, and/or user-defined clip planes prior to rasterization. ### Claim 6 (depends on 5) The graphics processing apparatus as in claim 5 wherein the clipping performed by the clipping circuit generates the convex polygon. ### Claim 7 (depends on 1) The graphics processing apparatus as in claim 1 wherein the rasterizer is to perform underestimating conservative rasterization or overestimating conservative rasterization using the first edge processing circuit and/or the second edge processing circuit. ### Claim 8 (depends on 1) The graphics processing apparatus as in claim 1 wherein the rasterizer is to perform hierarchical conservative rasterization using the first edge processing circuit and/or the second edge processing circuit. ### Claim 9 (depends on 8) The graphics processing apparatus as in claim 8 wherein performing hierarchical conservative rasterization comprises performing one or more trivial reject tests to reject image tiles which are entirely outside of any edge and one or more trivial accept tests to identify pixels within tiles that entirely inside of one or more edges. ### Claim 10 A method comprising: identifying edges of two or more triangles forming a convex polygon as inner edges or non-inner edges; and responsively performing rasterization of the two or more triangles using a first edge processing circuit that comprises logic and/or circuitry to implement a first edge test applied to center points of pixels overlapping inner edges and a second edge processing circuit that comprises logic and/or circuitry to implement a second edge test applied to corner points of pixels overlapping non-inner edges. ### Claim 11 (depends on 10) The method as in claim 10 wherein the second edge test is applied the corner points nearest the non-inner edges for an overestimating edge test or the second edge test is applied to the corner points farthest from the non-inner edges for an underestimating edge test. ### Claim 12 (depends on 11) The method as in claim 11 further comprising: a clipping or setup circuit to perform clipping or setup operations for the rasterizer, the edge tagging circuit to be integrated within the clipping or setup circuit. ### Claim 13 (depends on 12) The method as in claim 12 wherein the two or more triangles comprise a first triangle and a second triangle sharing an inner edge and wherein the first edge test implemented for the first and second triangles ensures that no pixels overlapping the inner edge are generated multiple times. ### Claim 14 (depends on 13) The method as in claim 13 wherein the clipping circuit clips the first and second triangles against a view frustum, guard bands, and/or user-defined clip planes prior to rasterization. ### Claim 15 (depends on 14) The method as in claim 14 wherein the clipping performed by the clipping circuit generates the convex polygon. ### Claim 16 (depends on 10) The method as in claim 10 wherein the rasterizer is to perform underestimating conservative rasterization or overestimating conservative rasterization using the first edge processing circuit and/or the second edge processing circuit. ### Claim 17 (depends on 10) The method as in claim 10 wherein the rasterizer is to perform hierarchical conservative rasterization using the first edge processing circuit and/or the second edge processing circuit. ### Claim 18 (depends on 17) The method as in claim 17 wherein performing hierarchical conservative rasterization comprises performing one or more trivial reject tests to reject image tiles which are entirely outside of any edge and one or more trivial accept tests to identify pixels within tiles that have not been rejected by the trivial reject tests. ### Claim 19 A system comprising: a memory to store instructions and data; a processor to execute the instructions and process the data; a graphics processor to perform graphics operations in response to graphics instructions; a network interface to receive and transmit data over a network; an interface for receiving user input from a mouse or cursor control device, the plurality of cores executing the instructions and processing the data responsive to the user input; the graphics processor comprising: an edge tagging circuit to identify edges of two or more triangles forming a convex polygon as inner edges or non-inner edges; and a rasterizer to responsively perform rasterization of the two or more triangles using a first edge processing circuit that comprises logic and/or circuitry to implement a first edge test applied to center points of pixels overlapping inner edges and a second edge processing circuit that comprises logic and/or circuitry to implement a second edge test applied to corner points of pixels overlapping non-inner edges. ### Claim 20 (depends on 19) The system as in claim 19 wherein the second edge test is applied the corner points nearest the non-inner edges for an overestimating edge test or the second edge test is applied to the corner points farthest from the non-inner edges for an underestimating edge test. ### Claim 21 (depends on 20) The system as in claim 20 further comprising: a clipping or setup circuit to perform clipping or setup operations for the rasterizer, the edge tagging circuit to be integrated within the clipping or setup circuit. ### Claim 22 (depends on 21) The system as in claim 21 wherein the two or more triangles comprise a first triangle and a second triangle sharing an inner edge and wherein the first edge test implemented for the first and second triangles ensures that no pixels overlapping the inner edge are generated multiple times. ### Claim 23 (depends on 22) The system as in claim 22 wherein the clipping circuit clips the first and second triangles against a view frustum, guard bands, and/or user-defined clip planes prior to rasterization. ### Claim 24 (depends on 23) The system as in claim 23 wherein the clipping performed by the clipping circuit generates the convex polygon. ### Claim 25 (depends on 19) The system as in claim 19 wherein the rasterizer is to perform underestimating conservative rasterization or overestimating conservative rasterization using the first edge processing circuit and/or the second edge processing circuit. ### Claim 26 (depends on 19) The system as in claim 19 wherein the rasterizer is to perform hierarchical conservative rasterization using the first edge processing circuit and/or the second edge processing circuit. ### Claim 27 (depends on 26) The system as in claim 26 wherein performing hierarchical conservative rasterization comprises performing one or more trivial reject tests to reject image tiles which are entirely outside of any edge and one or more trivial accept tests to identify pixels within tiles that have not been rejected by the trivial reject tests.