# US 2017/0287102 A1 · Link aggregator for an electronic display > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0287102 A1 - Document ID: US20170287102A1 - Status: Published application - Kind: A1 - Application number: 15/627,192 - Filed: 2017-06-19 - Published: 2017-10-05 - Earliest claimed: 2013-09-11 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: Sreeraman Anantharaman; Colin Whitby-Strevens - Web page: https://patentgrep.com/patent/US20170287102A1 ## CPC - G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining - G09G 5/006: {Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04)} - G09G 2352/00: Parallel handling of streams of display data - G09G 2370/12: Use of DVI or HDMI protocol in interfaces along the display data pipeline - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract Video data and auxiliary data may be sent between a processor and a display device via a single cable using a link aggregator. As such, the link aggregator may receive a first parallel signal that may include the video data and a second parallel signal that may include auxiliary data from the processor. The link aggregator may then send the first parallel signal and the second parallel signal as an aggregated signal to the display device. Upon receiving the aggregated signal at the display device, the link aggregator may de-aggregate the aggregated signal into the first parallel signal and the second parallel signal. The link aggregator may then send the first parallel signal and the second parallel signal to a timing controller of the display device, such that the timing controller may display the video data using the display device. ## Claims ### Claim 1 A transmitter circuitry configured to transmit video data and auxiliary data to a display device, wherein the transmitter circuitry comprises: an analog front end (AFE) circuitry configured to receive a first parallel signal comprising the video data and generate attenuation-compensated video data based on the first parallel signal; a deserializer circuitry configured to convert the attenuation-compensated video data to packetized video data; a first-in first-out (FIFO) circuitry configured to align the packetized video data according to an order; a de-skew circuitry configured to generate de-skewed video data that resolves one or more time delay differences between each lane of data output by the FIFO circuitry; and an aggregator circuitry configured to: receive the auxiliary data from a processor and the de-skewed video data from the de-skew circuitry; aggregate the de-skewed video data and the auxiliary data into a single serial signal; and transmit the single serial signal via a single cable to a display device. ### Claim 2 (depends on 1) The transmitter circuitry of claim 1, wherein the AFE circuitry is configured to compensate from one or more channel attenuation effects for each cable of a plurality of cables that transmitted the first parallel signal. ### Claim 3 (depends on 1) The transmitter circuitry of claim 1, comprising a voltage mode logic (VML) driver configured to convert the single serial signal into a VML signal. ### Claim 4 (depends on 1) The transmitter circuitry of claim 1, comprising a diplexer circuitry configured to control a transmission of the VML signal to the display device. ### Claim 5 (depends on 1) The transmitter circuitry of claim 1, comprising a power management circuitry configured to control one or more power operations of the transmitter circuitry based on traffic data related to the auxiliary data. ### Claim 6 (depends on 5) The transmitter circuitry of claim 5, wherein the one or more power operations comprise entering a sleep mode or powering down the transmitter circuitry. ### Claim 7 (depends on 1) The transmitter circuitry of claim 1, wherein the aggregator circuitry comprises: a first multiplexer circuitry configured to receive the de-skewed video data from the de-skew circuitry; a second multiplexer circuitry configured to receive the auxiliary data from the processor; and a decode circuitry configured to receive the auxiliary data via the second multiplexer, identify a blanking period in the auxiliary data, and send the auxiliary data and the blanking period to the first multiplexer. ### Claim 8 An aggregator circuitry configured to aggregate video data and auxiliary data, wherein the aggregator circuitry comprises: a first multiplexer circuitry configured to receive the auxiliary data; a decode circuitry configured to receive the auxiliary data via the first multiplexer and identify a blanking period in the auxiliary data; a second multiplexer circuitry configured to receive the auxiliary data and the blanking period via the decode circuitry and receive the video data, wherein the second multiplexer is configured to aggregate the video data and the auxiliary data using a time division scheme, thereby generating a multiplexed parallel signal; an error correction circuitry configured to adjust the multiplexed parallel signal for one or more errors associated with the aggregation of the video data and the auxiliary data, thereby generating an error-corrected parallel signal; a parallel-to-serial converter configured to convert the error-corrected parallel signal into a serial signal stream; and a diplexer configured to transmit the serial signal stream to a display device via a single cable. ### Claim 9 (depends on 8) The aggregator circuitry of claim 8, comprising a voltage mode logic (VML) driver configured to convert the serial signal stream to a VML signal; and send the VML signal to the diplexer, wherein the diplexer is configured to send the VML signal to the display device via the single cable. ### Claim 10 (depends on 8) The aggregator circuitry of claim 8, comprising a second decode circuitry configured to: receive a combined signal comprising a hot plug detect (HPD) signal and a second auxiliary signal from the display device; send the HPD signal to a processor; and send the second auxiliary signal to first multiplexer. ### Claim 11 (depends on 8) The aggregator circuitry of claim 8, wherein the first multiplexer is configured to control a direction in which data is transmitted. ### Claim 12 (depends on 8) The aggregator circuitry of claim 8, wherein the second multiplexer is configured to infer when to start aggregating the auxiliary data and the video data based on the blanking period. ### Claim 13 (depends on 8) The aggregator circuitry of claim 8, wherein the second multiplexer is configured to receive the video data as an 8b10b stream. ### Claim 14 (depends on 8) The aggregator circuitry of claim 8, wherein the second multiplexer is configured to align a plurality of lanes of the video data. ### Claim 15 A receiver circuitry configured to receive a serial signal stream comprising video data and auxiliary data, wherein the receiver circuitry comprises: a diplexer configured to receive the serial signal stream from a transmitter circuitry via a single cable; an analog front end (AFE) circuitry configured to receive the serial signal stream from the diplexer, wherein the AFE circuitry comprises an equalizer configured to compensate for one or more channel attenuation effects; an error detection and correction circuitry configured to receive an attenuation-compensated serial signal from the AFE circuitry, wherein the error detection and correction circuitry is configured to correct one or more errors in the attenuation-compensated serial signal; and a de-aggregator circuitry configured to receive an error-corrected serial signal from the error detection and correction circuitry and convert the error-corrected serial signal into the video data and the auxiliary data, wherein the video data is configured to be displayed via a display device. ### Claim 16 (depends on 15) The receiver circuitry of claim 15, wherein the diplexer is configured to control a direction in which data is transmitted. ### Claim 17 (depends on 15) The receiver circuitry of claim 15, wherein the equalizer comprises a continuous-time linear equalizer, a decision feedback equalizer, or both. ### Claim 18 (depends on 15) The receiver circuitry of claim 15, wherein the error detection and correction circuitry comprises a squelch circuit configured to detect in response to the attenuation-compensated serial signal being received from the AFE circuitry. ### Claim 19 (depends on 18) The receiver circuitry of claim 18, wherein the squelch circuit is configured to send a wake command to the error detection and correction circuitry in response to the attenuation-compensated serial signal being detected. ### Claim 20 (depends on 18) The receiver circuitry of claim 18, wherein the error detection and correction circuitry operates in a sleep mode or power off mode until the wake command is received.