# US 2017/0286590 A1 · Method and Apparatus for Performing Register Retiming in the Presence of Timing Analysis Exceptions > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0286590 A1 - Document ID: US20170286590A1 - Status: Published application - Kind: A1 - Application number: 15/626,089 - Filed: 2017-06-17 - Published: 2017-10-05 - Earliest claimed: 2015-02-20 - Assignees: Altera Corporation - Applicants: Altera Corporation - Inventors: Salem Derisavi; Gordon Raymond Chiu; Benjamin Gamsa - Web page: https://patentgrep.com/patent/US20170286590A1 ## CPC - G06F 30/3312: Timing analysis - G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist - G06F 30/331: with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation - G06F 2119/12: Timing analysis or timing optimisation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for register retiming. ## Claims ### Claim 1 A method for designing a system on a target device, comprising: identifying an area on the target device that includes components affected by a timing exception for a portion of a signal path; and performing register retiming where a register is moved from a first position on the signal path on one side of the area to a second position on the signal path on another side of the area. ### Claim 2 (depends on 1) The method of claim 1, wherein the timing exception for the portion of the signal path comprises a timing condition permitted for the portion of the signal path that is different from a default timing constraint applied to other portions of the signal path. ### Claim 3 (depends on 1) The method of claim 1, wherein the timing exception for the portion of the signal path comprises a timing condition permitted for the portion of the signal path that is different from a default timing constraint applied to other signal paths. ### Claim 4 (depends on 1) The method of claim 1, wherein the timing exception comprises a multicycle that identifies how a default timing constraint may be applied differently to the portion of the signal path. ### Claim 5 (depends on 1) The method of claim 1, wherein the timing exception comprises a false path that excuses a default timing constraint from being applied to the portion of the signal path. ### Claim 6 (depends on 1) The method of claim 1, wherein the timing exception comprises a minimum delay and maximum delay for a signal on the portion of the signal path. ### Claim 7 (depends on 1) The method of claim 1, wherein identifying the area that includes components affected by the timing exception comprises: identifying a first component at a beginning of the timing exception; identifying a second component at an end of the timing exception; and defining the area to include the first component, the second component, and all components along the portion of the path between the first and second components. ### Claim 8 (depends on 1) The method of claim 1 further comprising: identifying a second timing exception for a second portion of the signal path; identifying a second area on the target device that includes components affected by the second timing exception, wherein the first position on the signal path is on one side of the second area and the second position on the signal path is on another side of the second area. ### Claim 9 (depends on 1) The method of claim 1, wherein the register retiming reallocates delay along the signal path to allow a signal to satisfy timing requirements along the signal path. ### Claim 10 (depends on 1) The method of claim 1, wherein the timing exception is provided by a user after timing analysis is performed on the system. ### Claim 11 (depends on 1) The method of claim 1, wherein the timing exception is provided during design entry prior to synthesis, placement, and routing of the system. ### Claim 12 (depends on 1) The method of claim 1, wherein register retiming is performed after synthesis, placement, and routing is performed on the system. ### Claim 13 (depends on 1) The method of claim 1 further comprising generating constraints that prevent registers residing in the area from being used for register retiming, wherein at least one of the identifying and generating is performed by a processor. ### Claim 14 A non-transitory computer readable medium including a sequence of instructions stored thereon for causing a computer to execute a method for designing a system on a target device, comprising: identifying an area on the target device that includes components affected by a timing exception for a portion of a signal path; and generating constraints that prevent registers residing in the area from being used for register retiming. ### Claim 15 (depends on 14) The non-transitory computer readable medium of claim 14 further comprising performing register retiming where a register is moved from a first position on the signal path on one side of the area to a second position on the signal path on another side of the area. ### Claim 16 (depends on 14) The non-transitory computer readable medium of claim 14, wherein the timing exception for the portion of the signal path comprises a timing condition permitted for the portion of the signal path that is different from a default timing constraint applied to other portions of the signal path. ### Claim 17 (depends on 14) The non-transitory computer readable medium of claim 14, wherein the timing exception comprises a multicycle that identifies how a default timing constraint may be applied differently to the portion of the signal path. ### Claim 18 (depends on 14) The non-transitory computer readable medium of claim 14, wherein the timing exception comprises a false path that excuses a default timing constraint from being applied to the portion of the signal path. ### Claim 19 (depends on 14) The non-transitory computer readable medium of claim 14, wherein the timing exception comprises a minimum delay and maximum delay for a signal on the portion of the signal path. ### Claim 20 (depends on 15) The non-transitory computer readable medium of claim 15 further comprising generating a report that identifies the register and the timing exception to a user. ### Claim 21 A system designer, comprising: an area identification unit that identifies an area in a system that includes a first component at a beginning of a timing exception for a portion of a signal path, a second component at an end of the timing exception, and all components along the signal path between the first and the second components; and a register retiming unit that performs register retiming where a register is moved from a first position on the signal path on one side of the area to a second position on the signal path on another side of the area. ### Claim 22 (depends on 21) The system designer of claim 21 further comprising a constraints unit that applies constraints to unallocated registers in the area to prevent the unallocated registers to be used in register retiming. ### Claim 23 (depends on 21) The system designer of claim 21, wherein the timing exception for the portion of the signal path comprises a timing condition permitted for the portion of the signal path that is different from a default timing constraint applied to other portions of the signal path. ### Claim 24 (depends on 21) The method of claim 21, wherein the register retiming is performed after synthesis, placement, and routing is performed on the system.