# US 2017/0286582 A1 · Efficient integrated circuits configuration data mangement > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0286582 A1 - Document ID: US20170286582A1 - Status: Published application - Kind: A1 - Application number: 15/489,305 - Filed: 2017-04-17 - Published: 2017-10-05 - Earliest claimed: 2015-08-27 - Assignees: Altera Corporation - Applicants: Altera Corporation - Inventors: Junaid Asim Khan; Scott James Brissenden - Web page: https://patentgrep.com/patent/US20170286582A1 ## CPC - G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] - G06F 15/7867: {with reconfigurable architecture} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Circuitry for efficient configuration data management is presented. The circuitry may include an encoding circuit that compares the configuration data of a circuit design with the base configuration data of a base circuit design. The encoding circuit may compress the difference between the configuration data and the base configuration data to produce compressed configuration data. The compressed configuration data may be stored in a storage circuit. For the purpose of implementing the circuit design in an integrated circuit, a decoding circuit may retrieve the compressed configuration data from the storage circuit, decompress the compressed configuration data, and compare the result of the decompression operation with the base configuration data to restore the configuration data. The restored configuration data may serve to program configuration memory bits on the integrated circuit, thereby implementing the circuit design. ## Claims ### Claim at position 1 1-25. (canceled) ### Claim 26 A tangible, non-transitory, machine-readable medium, comprising machine readable instructions, to: generate a bit file configured to program a base configuration of a field programmable gate array (FPGA); access a stored indication of a placement, a routing, or both for one or more modifications to at least a portion of the base configuration, generate a partial bit file configured to modify the at least portion of the base configuration with the one or more modifications, in accordance with the indication of the placement, the routing or both; and provide the partial bit file to the FPGA for subsequent implementation of the one or more modifications on the FPGA. ### Claim 27 (depends on 26) The machine-readable medium of claim 26, comprising machine-readable instructions, to: compress the partial bit file after it is generated. ### Claim 28 (depends on 26) The machine-readable medium of claim 26, comprising machine-readable instructions, to: decompress the partial bit file prior to providing the partial bit file to the FPGA. ### Claim 29 (depends on 28) The machine-readable medium of claim 28, comprising machine-readable instructions, to: decompress the partial bit file using entropy decoding. ### Claim 30 (depends on 28) The machine-readable medium of claim 28, wherein the entropy decoding comprises Huffman decoding, arithmetic decoding, universal decoding, Golomb decoding, or any combination thereof. ### Claim 31 A method, comprising: programming, using a first received bit file, a field programmable gate array (FPGA) with a base configuration indicated by the bit file; and subsequently programming the FPGA with modifications to a portion of the base configuration, using a second received partial bit file, wherein the second received partial bit file was previously generated based upon an accessed stored indication of a corresponding placement, routing, or both. ### Claim 32 (depends on 31) The method of claim 31, wherein the second received partial bit file is compressed as a compressed partial bit file prior to subsequently configuring the modification to a portion of the base configuration and corresponding placement, routing, or placement and routing on the FPGA. ### Claim 33 (depends on 31) The method of claim 31, wherein the compressed partial bit file is decompressed prior to subsequently configuring the modification to a portion of the base configuration and corresponding placement, routing, or placement and routing on the FPGA. ### Claim 34 (depends on 31) The method of claim 31, wherein the compressed partial bit file is decompressed using entropy decoding. ### Claim 35 (depends on 31) The method of claim 31, wherein the compressed partial bit file is decompressed using entropy decoding comprises Huffman decoding, arithmetic decoding, universal decoding, Golomb decoding, or any combination thereof. ### Claim 36 A system for implementing designs for an FPGA, comprising instructions stored on a tangible, non-transitory, machine-readable medium, configured to: generate a bit file that defines a base configuration of the FPGA; cause transmission of the bit file to the FPGA; access a stored indication of a placement, a routing, or both for one or more modifications to at least a portion of the base configuration; generate a partial bit file comprising an indication of modifications to a portion of the base configuration to a portion of the base configuration, in accordance with the stored indication of the placement, the routing, or both for the modifications, and cause transmission of the partial bit file to the FPGA to implement the modifications to the portion of the base configuration. ### Claim 37 (depends on 36) The system of claim 36, comprising instructions stored on the tangible, non-transitory, machine-readable medium, configured to compress the partial bit file after it is generated. ### Claim 38 (depends on 37) The system of claim 37, comprising instructions stored on the tangible, non-transitory, machine-readable medium, configured to decompress the partial bit file prior to causing transmission of the partial bit file to the FPGA. ### Claim 39 (depends on 38) The system of claim 38, comprising instructions stored on the tangible, non-transitory, machine-readable medium, configured to decompress the partial bit file using entropy decoding. ### Claim 40 (depends on 39) The system of claim 39, wherein the entropy decoding comprises: Huffman decoding, arithmetic decoding, universal decoding, Golomb decoding, or any combination thereof. ### Claim 41 A system, comprising: a programmable device that is selectively programmable to implement a first circuit design and a second circuit design; and one or more hardware-based processors configured to: generate a first bit file that defines a base circuit design for the programmable device; access a stored indication of a first placement, a first routing, or both of the first circuit design; generate a second bit file that defines the first circuit design implemented via one or more first modifications of the base circuit design, in accordance with the indication of the first placement, the first routing, or both; and access a stored indication of a second placement, a second routing, or both of a the second circuit design; and generate a third bit file that defines the second circuit design implemented via one or more second modifications of the base circuit design, in accordance with the indication of the second placement, the second routing, or both. ### Claim 42 (depends on 41) The system of claim 41, wherein the one or more hardware-based processors are configured to: cause implementation of the first bit file on the programmable device; upon receiving a request to implement the first circuit design on the programmable device, cause implementation of one or more first modifications of the base circuit design according to the first placement, first routing, or both; and upon receiving a request to implement the second circuit design on the programmable device, cause implementation of one or more second modifications of the base circuit design according to the second placement, second routing, or both. ### Claim 43 (depends on 42) The system of claim 42, comprising a tangible, non-transitory machine-readable medium; wherein the one or more hardware-based processors are configured to compress the second bit file, the third bit file or both for storage on the tangible, non-transitory, machine-readable medium. ### Claim 44 (depends on 43) The system of claim 43, wherein the one or more hardware-based processors are configured to, upon receiving a request to implement the first circuit design on the programmable device, decompress the second bit file. ### Claim 45 (depends on 43) The system of claim 43, wherein the one or more hardware-based processors are configured to, upon receiving a request to implement the second circuit design on the programmable device, decompress the third bit file.