# US 2017/0286358 A1 · Sensor bus communication system

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- Number: US 2017/0286358 A1
- Document ID: US20170286358A1
- Status: Published application
- Kind: A1
- Application number: 15/086,700
- Filed: 2016-03-31
- Published: 2017-10-05
- Earliest claimed: 2016-03-31
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Amit Kumar Srivastava
- Web page: https://patentgrep.com/patent/US20170286358A1

## CPC

- G06F 13/4291: {using a clocked protocol}
- G06F 1/324: by lowering clock frequency
- G06F 13/1673: {using buffers}
- G06F 13/364: using independent requests or grants, e.g. using separated request and grant lines
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Described is an I3C Repeater. The I3C Repeater may have a first circuitry with an I3C interface, a second circuitry with an I2C interface, and a datapath circuitry coupled to the first circuitry and the second circuitry. The second circuitry may be operable to convert a transaction received on the I2C interface into a transaction for the I3C interface, and to convert a transaction received on the I3C interface into a transaction for the I2C interface. The I3C Repeater may also have additional circuitries operable to convert transactions received on one of an SPI interface, a UART interface, and a Debug bus interface into transactions for the I3C interface, and vice-versa.

## Claims

### Claim 1

An apparatus comprising:
a first circuitry comprising a first input/output (IO) interface;
a second circuitry comprising a second input/output (IO) interface; and
a datapath circuitry coupled to the first circuitry and the second circuitry,
wherein the second circuitry is to convert a transaction received on the second IO interface into a transaction for the first IO interface, and to convert a transaction received on the first IO interface into a transaction for the second IO interface; and
wherein the first IO interface comprises a serial data bus which is operable at a first frequency, and the second IO interface comprises a serial data bus which is operable at a second frequency, the first frequency being greater than the second frequency.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the second IO interface is an Inter Integrated Circuit (I2C) interface.

### Claim 3 (depends on 1)

The apparatus of claim 1, comprising:
a third circuitry comprising a third input/output (IO) interface,
wherein the third circuitry is to convert a transaction received on the third IO interface into a transaction for the first IO interface, and to convert a transaction received on the first IO interface into a transaction for the third IO interface.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the third IO interface is one of: a Serial Peripheral Interface (SPI) bus, a UART (Universal Asynchronous Receiver/Transmitter) bus, and a debug bus.

### Claim 5 (depends on 3)

The apparatus of claim 3,
wherein the datapath circuitry is to forward a transaction received on the second IO interface to the first circuitry, and is to forward a transaction received on the third IO interface to the first circuitry; and
wherein the datapath circuitry is to arbitrate between a transaction received on the second IO interface and a transaction received on the third IO interface.

### Claim 6 (depends on 1)

The apparatus of claim 1, comprising an internal oscillator.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the first IO interface is operable at a first high-voltage level, and the second IO interface is operable at a second high-voltage level greater than the first high-voltage level.

### Claim 8 (depends on 7)

The apparatus of claim 7,
wherein the second circuitry has a first part operable at the first frequency and at the first high-voltage level, and has a second part operable at the second frequency and at the second high-voltage level; and
wherein the first part is driven by a first clock source and a first supply voltage, and the second part is driven by a second clock source separate from the first clock source and a second supply voltage separate from the first supply voltage.

### Claim 9 (depends on 1)

The apparatus of claim 1,
wherein the second circuitry is to write a first transaction received to a buffer at the first frequency, and is to retrieve the first transaction from the buffer at the second frequency; and
wherein the second circuitry is to write a second transaction received to a buffer at the second frequency, and is to retrieve the second transaction from the buffer at the first frequency.

### Claim 10 (depends on 1)

The apparatus of claim 1,
wherein the second circuitry is to map one or more fields of a first transaction compliant with the first IO interface into one or more fields for a transaction compliant with the second IO interface; and
wherein the second circuitry is to map one or more fields of a second transaction compliant with the second IO interface into one or more fields for a transaction compliant with the first IO interface.

### Claim 11

An apparatus comprising:
a host-protocol transceiver coupled to a host-protocol input/output (IO) interface comprising a serial data bus;
a first guest-protocol transceiver coupled to a first guest-protocol input/output (IO) interface comprising a serial data bus; and
a second guest-protocol transceiver coupled to a second guest-protocol input/output (IO) interface,
wherein the serial data bus of the host-protocol IO interface is operable at a first frequency, and the serial data bus of the first guest-protocol IO interface is operable at a second frequency, the first frequency being greater than the second frequency; and
wherein the host-protocol IO interface is operable at a first high-voltage level, and the first guest-protocol IO interface is operable at a second high-voltage level, the second high-voltage level being greater than the first high-voltage level.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the first guest-protocol IO interface is an Inter Integrated Circuit (I2C) interface.

### Claim 13 (depends on 11)

The apparatus of claim 11, wherein the second guest-protocol IO interface is one of: a Serial Peripheral Interface (SPI) interface, a Universal Asynchronous Receiver/Transmitter (UART) interface, and a Debug Bus interface.

### Claim 14 (depends on 11)

The apparatus of claim 11, comprising:
a first guest-protocol conversion circuitry to convert a transaction received by the first guest-protocol transceiver into a first converted transaction for the host-protocol transceiver, and to convert a transaction received by the host-protocol transceiver into a transaction for the first guest-protocol transceiver; and
a second guest-protocol conversion circuitry to convert a transaction received by the second guest-protocol transceiver into a second converted transaction for the host-protocol transceiver, and to convert a transaction received by the host-protocol transceiver into a transaction for the second guest-protocol transceiver.

### Claim 15 (depends on 14)

The apparatus of claim 14, comprising:
a first datapath circuitry to forward the first converted transaction for the host-protocol transceiver to the host-protocol transceiver; and
a second datapath circuitry to forward the second converted transaction for the host-protocol transceiver to the host-protocol transceiver.

### Claim 16 (depends on 15)

The apparatus of claim 15, comprising:
a bus selection circuitry to select between the first datapath circuitry and the second datapath circuitry based upon an assigned priority of the first guest-protocol IO interface and an assigned priority of the second guest-protocol IO interface.

### Claim 17 (depends on 11)

The apparatus of claim 11, comprising
a first guest-protocol conversion circuitry to convert a transaction received by the first guest-protocol transceiver into a transaction for the host-protocol transceiver, and to convert a transaction received by the host-protocol transceiver into a transaction for the first guest-protocol transceiver,
wherein the first guest-protocol conversion circuitry has a first part operable at the first frequency and at the first high-voltage level, and has a second part operable at the second frequency and at the second high-voltage level; and
wherein the first part is driven by a first clock source and a first supply voltage, and the second part is driven by a second clock source separate from the first clock source and a second supply voltage separate from the first supply voltage.

### Claim 18 (depends on 11)

The apparatus of claim 11, wherein the host-protocol IO interface comprises a serial clock line and a serial data line.

### Claim 19

The apparatus of 14,
wherein the first guest-protocol conversion circuitry is to buffer a first transaction received at the first frequency, and is to retrieve the first transaction at the second frequency; and
wherein the first guest-protocol conversion circuitry is to buffer a second transaction received at the second frequency, and is to receive the second transaction at the second frequency.

### Claim 20 (depends on 14)

The apparatus of claim 14,
wherein the first guest-protocol conversion circuitry is to map one or more fields of a first transaction compliant with the host-protocol IO interface into one or more fields for a transaction compliant with the first guest-protocol IO interface; and
wherein the first guest-protocol conversion circuitry is to map one or more fields of a second transaction compliant with the first guest-protocol IO interface into one or more fields for a transaction compliant with the host-protocol IO interface.

### Claim 21

A system comprising a memory, a processor coupled to the memory, and a wireless interface for allowing the processor to communicate with another device, the processor and a repeater including:
a first circuitry comprising a first input/output (IO) interface;
a second circuitry comprising a second input/output (IO) interface; and
a datapath circuitry coupled to the first circuitry and the second circuitry,
wherein the second circuitry is to convert a transaction received on the second IO interface into a transaction for the first IO interface, and to convert a transaction received on the first IO interface into a transaction for the second IO interface; and
wherein the first IO interface comprises a serial data bus which is operable at a first frequency, and the second IO interface comprises a serial data bus which is operable at a second frequency, the first frequency being greater than the second frequency.

### Claim 22 (depends on 21)

The system of claim 21, comprising:
a third circuitry comprising a third input/output (IO) interface,
wherein the third circuitry is to convert a transaction received on the third IO interface into a transaction for the first IO interface, and to convert a transaction received on the first IO interface into a transaction for the third IO interface.

### Claim 23 (depends on 21)

The system of claim 21,
wherein the datapath circuitry is to forward a transaction received on the second IO interface to the first circuitry, and is to forward a transaction received on the third IO interface to the first circuitry; and
wherein the datapath circuitry is to arbitrate between a transaction received on the second IO interface and a transaction received on the third IO interface.