# US 2017/0286341 A1 · Communication system, communication system control method, and program > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0286341 A1 - Document ID: US20170286341A1 - Status: Published application - Kind: A1 - Application number: 15/623,230 - Filed: 2017-06-14 - Published: 2017-10-05 - Earliest claimed: 2015-10-01 - Assignees: Sony Corporation - Applicants: Sony Corporation - Inventors: Hiroo Takahashi; Naohiro Koshisaka; Sonfun Lee - Web page: https://patentgrep.com/patent/US20170286341A1 ## CPC - G06F 13/364: using independent requests or grants, e.g. using separated request and grant lines - G06F 13/362: with centralised access control - G06F 13/404: {with address mapping} - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F 13/4291: {using a clocked protocol} - G06F 2213/0052: Assignment of addresses or identifiers to the modules of a bus system - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Communication systems and communication control methods are disclosed. In one example, a slave device belonging to a group of devices to which arbitration is applicable sequentially transmits a start bit and a first address including a first bit having a value different from a corresponding first bit of predetermined pattern data. A master device sequentially transmits the start bit and the predetermined pattern data. The master device arbitrates the master device and the first slave device based on the value of the first bit. ## Claims ### Claim 1 A master device comprising: a communication circuitry configured to sequentially transmit a start bit indicating communication start, predetermined pattern data, and an address in which inclusion or non-inclusion in a group for which arbitration is necessary is set in a first bit; and an arbitration circuitry configured to arbitrate a slave device and another device based on the first bit. ### Claim 2 (depends on 1) The master device according to claim 1, wherein the communication circuitry receives an acknowledgment after the start bit and the predetermined pattern data are sequentially transmitted, transmits a restart condition indicating communication restart, and transmits the address. ### Claim 3 (depends on 1) The master device according to claim 1, wherein, when a value different from a first bit of the predetermined pattern data is detected in the arbitration based on the first bit performed by the arbitration circuitry, the communication circuitry determines that an event that includes an in-band interrupt request, a secondary master request, or a peer to peer slave request and for which arbitration is necessary has occurred and stops transmission of the predetermined pattern data, wherein the arbitration circuitry receives an address of second and subsequent bits from the slave device and performs arbitration in units of bits, and wherein the communication circuitry transmits an acknowledgment, and then transmits and receives data or performs a processing of data when the master device is able to accept the event, and ends a communication process without transmitting the acknowledgment when the master device is unable to accept the event. ### Claim 4 (depends on 1) The master device according to claim 1, wherein the device to which an address in which inclusion or non-inclusion in a group for which arbitration is necessary is set in a first bit is allocated. ### Claim 5 (depends on 1) The master device according to claim 1, further comprising: address allocation circuitry configured to allocate a first address and a second address based upon setting information, wherein the first address indicates inclusion in the group for which arbitration is necessary and the second address indicates non-inclusion in the group for which arbitration is necessary. ### Claim 6 (depends on 1) The master device according to claim 1, wherein the slave device is configurable as an arbitration target slave device for which arbitration is necessary and an arbitration-unnecessary slave device for which arbitration is unnecessary, and wherein the master device comprises address allocation circuitry configured to allocate addresses to the arbitration target slave device and the arbitration-unnecessary slave device such that a bit string except for a first bit of an arbitration target slave device address is different from the bit string except for the first bit of an arbitration-unnecessary slave device address. ### Claim 7 (depends on 1) The master device according to claim 1, wherein the predetermined pattern indicates a reserved condition, and the address is a dynamically assigned address that is transmitted following transmission of the predetermined pattern. ### Claim 8 (depends on 7) The master device according to claim 7, wherein the communication circuitry is configured to transmit the predetermined pattern in an open drain circuit mode. ### Claim 9 (depends on 1) The master device according to claim 1, further comprising: address allocation circuitry configured to perform a dynamic addressing wherein the first bit of the address is set to a predetermined value, and wherein the arbitration circuitry is configured to perform arbitration by determining collision in the first bit where the master device receives from the slave device a slave device address having a first bit with a value differing from the predetermined value. ### Claim 10 (depends on 9) The master device according to claim 9, wherein the communication circuitry is configured to transmit in a push-pull mode in an absence of determining collision. ### Claim 11 (depends on 1) The master device according to claim 1, wherein the master device is configured to receive from the slave device a first address wherein the first bit indicates inclusion or non-inclusion in the group for which arbitration is necessary, and wherein the arbitration circuitry is configured to arbitrate the master device and the slave device based on the value of the first bit in the first address. ### Claim 12 (depends on 1) The master device according to claim 1, further comprising: address allocation circuitry configured to assign addresses wherein the first bit of the address is set to a first predetermined value indicative of master side addressing, and wherein addresses assignable by slave devices have the first bit of the address set to a second predetermined value that differs from the first predetermined value and that is indicative of slave side addressing. ### Claim 13 (depends on 12) The master device according to claim 12, wherein the master device is configured to receive an acknowledgement from the slave device following transmission of an assigned address to the slave device by the master device.