# US 2017/0286334 A1 · Enhanced directed system management interrupt mechanism

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- Number: US 2017/0286334 A1
- Document ID: US20170286334A1
- Status: Published application
- Kind: A1
- Application number: 15/088,429
- Filed: 2016-04-01
- Published: 2017-10-05
- Earliest claimed: 2016-04-01
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Gaurav Khanna; Prashant Sethi; Venkatesh Ramamurthy
- Web page: https://patentgrep.com/patent/US20170286334A1

## CPC

- G06F 13/24: using interrupt (G06F13/32 takes precedence)
- G06F 1/3206: Monitoring of events, devices or parameters that trigger a change in power modality
- G06F 9/4418: {Suspend and resume; Hibernate and awake}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method is described. The method includes determining that a first of a plurality of processor cores in a multi-processor computing system has entered an idle state, triggering a SMI for the first processor core, the first processor core entering a system management mode (SMM) and performing one or more platform management operations.

## Claims

### Claim 1

A compute node comprising:
a plurality of processor cores, each including;
an operating system (OS) having an OS power management (OSPM) engine to determine that a first of the plurality of processor cores has entered an idle state; and
a system management mode (SMM) handler to detect a system management interrupt (SMI) and transition control of hardware resources of the first processor core from the OS to a basic input output system (BIOS) to enter a system management mode (SMM) in order to perform one or more platform management operations.

### Claim 2 (depends on 1)

The compute node of claim 1, wherein the SMM handler detects an event indicating an operating system (OS) is to resume control of the first processor core and exits the SMM to restore control of the OS.

### Claim 3 (depends on 2)

The compute node of claim 2, wherein the event indicates that the first processor core is an interrupt destination from an input/output (I/O) device.

### Claim 4 (depends on 2)

The compute node of claim 2, wherein the event indicates that the first processor core is a destination of a scheduler dispatch interrupt from a second of the plurality of processor cores.

### Claim 5 (depends on 2)

The compute node of claim 2, wherein the event indicates that the first processor core is destination for a Translation Lookaside Buffer (TLB) flush inter-processor interrupt (IPI).

### Claim 6 (depends on 1)

The compute node of claim 1, wherein the OSPM engine determines that the first processor core has re-entered the idle state.

### Claim 7 (depends on 6)

The compute node of claim 6, wherein the SMM handler detects a second SMI and re-enters the SMM in order to resume performance of the one or more platform management operations.

### Claim 8 (depends on 1)

The compute node of claim 1, wherein the SMM is exited within a predetermined time threshold.

### Claim 9 (depends on 1)

The compute node of claim 1, wherein the OSPM monitors the first processor core to determine whether the core is ready to enter the idle state and cause the first processor core to enter the idle state.

### Claim 10

A directed system management interrupt (SMI) method comprising:
determining that a first of a plurality of processor cores in a multi-processor computing system has entered an idle state;
triggering a SMI for the first processor core;
the first processor core entering a system management mode (SMM); and
performing one or more platform management operations.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
detecting an event indicating an operating system (OS) is to resume control of the first processor core; and
exiting the SMM.

### Claim 12 (depends on 11)

The method of claim 11, wherein the event indicates that the first processor core is an interrupt destination from an input/output (I/O) device.

### Claim 13 (depends on 11)

The method of claim 11, wherein the event indicates that the first processor core is a destination of a scheduler dispatch interrupt from a second of the plurality of processor cores.

### Claim 14 (depends on 11)

The method of claim 11, wherein the event indicates that the first processor core is destination for a Translation Lookaside Buffer (TLB) flush inter-processor interrupt (IPI).

### Claim 15 (depends on 10)

The method of claim 10, further comprising:
determining that the first processor core has re-entered the idle state;
triggering the SMI for the first processor core;
the first processor core re-entering the SMM; and
resuming performance of the one or more platform management operations.

### Claim 16 (depends on 10)

The method of claim 10, wherein the SMM is exited within a predetermined time threshold.

### Claim 17 (depends on 10)

The method of claim 10, further comprising:
monitoring the first processor core to determine whether the core is ready to enter the idle state; and
causing the first processor core to enter the idle state.

### Claim 18

At least one computer readable medium having instructions, which when executed by one or more processors, cause the processors to:
determine that a first of a plurality of processor cores in a multi-processor computing system has entered an idle state;
trigger a SMI for the first processor core;
enter the first processor core into a system management mode (SMM); and
perform one or more platform management operations.

### Claim 19 (depends on 18)

The computer readable medium of claim 18, having instructions, which when executed by the one or more processors, further cause the processors to:
detect an event indicating an operating system (OS) is to resume control of the first processor core; and
exit the SMM.

### Claim 20 (depends on 19)

The computer readable medium of claim 19, wherein the event indicates that the first processor core is an interrupt destination from an input/output (I/O) device.

### Claim 21 (depends on 19)

The computer readable medium of claim 19, wherein the event indicates that the first processor core is a destination of a scheduler dispatch interrupt from a second of the plurality of processor cores.

### Claim 22 (depends on 19)

The computer readable medium of claim 19, wherein the event indicates that the first processor core is destination for a Translation Lookaside Buffer (TLB) flush inter-processor interrupt (IPI).

### Claim 23 (depends on 18)

The computer readable medium of claim 18, having instructions, which when executed by the one or more processors, further cause the processors to:
determine that the first processor core has re-entered the idle state;
trigger the SMI for the first processor core;
re-enter the first processor core the SMM; and
resume performance of the one or more platform management operations.

### Claim 24 (depends on 18)

The computer readable medium of claim 18, wherein the SMM is exited within a predetermined time threshold.

### Claim 25 (depends on 18)

The computer readable medium of claim 18, having instructions, which when executed by the one or more processors, further cause the processors to:
monitor the first processor core to determine whether the core is ready to enter the idle state; and
cause the first processor core to enter the idle state.