# US 2017/0286332 A1 · Technologies for processor core soft-offlining > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0286332 A1 - Document ID: US20170286332A1 - Status: Published application - Kind: A1 - Application number: 15/083,961 - Filed: 2016-03-29 - Published: 2017-10-05 - Earliest claimed: 2016-03-29 - Assignees: Intel Corporation - Inventors: Karunakara Kotary; Gaurav Khanna; Abhinav R. Karhu - Web page: https://patentgrep.com/patent/US20170286332A1 ## CPC - G06F 13/24: using interrupt (G06F13/32 takes precedence) - G06F 9/4401: Bootstrapping (security arrangements therefor G06F21/57) - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Technologies for processor core soft-offlining include a computing device having a processor with multiple processor cores. On boot, an operating system queries a firmware interface to retrieve a potential offline set of processor cores. The operating system prevents the processor cores of the potential offline set from receiving device interrupts. The computing device detects a platform management event from the firmware interface and, in response to the platform management event, queries the firmware interface to determine a requested offline set of processor cores. Each of the processor cores in the requested offline set is included in the potential offline set. The computing device brings the processor cores of the requested offline set into a low-power state, and then the computing device may start performing a platform management operation. The platform management event may include a memory hot-plug event or a specialized workload event. Other embodiments are described and claimed. ## Claims ### Claim 1 A computing device for processor core offlining, the computing device comprising: a configuration module to query a firmware interface of the computing device to retrieve a first set of processor cores of the computing device, wherein each of the first set of processor cores is a potential target to soft-offline; an interrupt management module to prevent receipt of device interrupts by the processor cores of the first set of processor cores; and a core management module to (i) detect, in response to prevention of receipt of device interrupts by the processor cores of the first set of processor cores, a platform management event from the firmware interface and (ii) query the firmware interface to determine a second set of processor cores to bring offline in response to detection of the platform management event, wherein the second set of processor cores is included in the first set of processor cores. ### Claim 2 (depends on 1) The computing device of claim 1, wherein to query the firmware interface of the computing device to retrieve the first set of processor cores of the computing device comprises to evaluate an object of a firmware namespace established by the firmware environment of the computing device. ### Claim 3 (depends on 2) The computing device of claim 2, wherein to evaluate the object of the firmware namespace comprises to interpret a control method for a virtual machine with a bytecode interpreter of the computing device. ### Claim 4 (depends on 1) The computing device of claim 1, wherein to query the firmware interface to determine the second set of processor cores to bring offline comprises to evaluate an object of a firmware namespace established by the firmware environment of the computing device. ### Claim 5 (depends on 1) The computing device of claim 1, wherein the platform management event comprises a memory hot-plug event. ### Claim 6 (depends on 1) The computing device of claim 1, wherein the platform management event comprises a specialized workload event. ### Claim 7 (depends on 1) The computing device of claim 1, further comprising: a scheduler module to re-assign any threads from the second set of processor cores to one or more processor cores of the computing device not in the second set of processor cores; wherein the core management module is further to (i) bring the second set of processor cores into a low-power state in response to re-assignment of any threads and (ii) notify the firmware interface with the second set of processor cores in response to bringing of the second set of processor cores into the low-power state; and wherein the interrupt management module is further to prevent interrupts to the second set of processor cores in response to bringing of the second set of processor cores into the low-power state. ### Claim 8 (depends on 7) The computing device of claim 7, further comprising a platform management module to perform a platform management operation in response to notification of the firmware interface with the second set of processor cores. ### Claim 9 (depends on 8) The computing device of claim 8, wherein to perform the platform management operation comprises to enter, by each processor core of the second set of processor cores, a system management mode. ### Claim 10 (depends on 8) The computing device of claim 8, wherein to perform the platform management operation comprises to perform a specialized workload while the second set of processor cores are in the low-power state. ### Claim 11 (depends on 10) The computing device of claim 10, wherein to perform the specialized workload comprises to activate a non-core resource of a processor of the computing device. ### Claim 12 (depends on 8) The computing device of claim 8, wherein the core management module is further to: notify, by the firmware interface of the computing device, an operating system of the computing device in response to performance of the platform management operation to indicate that the platform management operation is completed; query the firmware interface to determine a third set of processor cores to bring online in response to notification of the operating system, wherein the third set of processor cores is included in the first set of processor cores; and bring the third set of processor cores into a normal power state. ### Claim 13 (depends on 12) The computing device of claim 12, wherein to query the firmware interface to determine the third set of processor cores to bring online comprises to evaluate an object of a firmware namespace established by the firmware environment of the computing device. ### Claim 14 A method for processor core offlining, the method comprising: querying, by a computing device, a firmware interface of the computing device to retrieve a first set of processor cores of the computing device, wherein each of the first set of processor cores is a potential target for soft-offlining; preventing, by the computing device, the processor cores of the first set of processor cores from receiving device interrupts; detecting, by the computing device in response to preventing the processor cores of the first set of the processor cores from receiving device interrupts, a platform management event from the firmware interface; and querying, by the computing device, the firmware interface to determine a second set of processor cores to bring offline in response to detecting the platform management event, wherein the second set of processor cores is included in the first set of processor cores. ### Claim 15 (depends on 14) The method of claim 14, further comprising: re-assigning, by the computing device, any threads from the second set of processor cores to one or more processor cores of the computing device not in the second set of processor cores; bringing, by the computing device, the second set of processor cores into a low-power state in response to re-assigning any threads; notifying, by the computing device, the firmware interface with the second set of processor cores in response to bringing the second set of processor cores into the low-power state; and preventing, by the computing device, interrupts to the second set of processor cores in response to bringing the second set of processor cores into the low-power state. ### Claim 16 (depends on 15) The method of claim 15, further comprising performing, by the computing device, a platform management operation in response to notifying the firmware interface with the second set of processor cores. ### Claim 17 (depends on 16) The method of claim 16, wherein performing the platform management operation comprises entering, by each processor core of the second set of processor cores, a system management mode. ### Claim 18 (depends on 16) The method of claim 16, wherein performing the platform management operation comprises performing a specialized workload while the second set of processor cores are in the low-power state. ### Claim 19 (depends on 16) The method of claim 16, further comprising: notifying, by the firmware interface of the computing device, an operating system of the computing device in response to performing the platform management operation to indicate that the platform management operation is completed; querying, by the computing device, the firmware interface to determine a third set of processor cores to bring online in response to notifying the operating system, wherein the third set of processor cores is included in the first set of processor cores; and bringing, by the computing device, the third set of processor cores into a normal power state. ### Claim 20 One or more computer-readable storage media comprising a plurality of instructions that in response to being executed cause a computing device to: query a firmware interface of the computing device to retrieve a first set of processor cores of the computing device, wherein each of the first set of processor cores is a potential target for soft-offlining; prevent the processor cores of the first set of processor cores from receiving device interrupts; detect, in response to preventing the processor cores of the first set of the processor cores from receiving device interrupts, a platform management event from the firmware interface; and query the firmware interface to determine a second set of processor cores to bring offline in response to detecting the platform management event, wherein the second set of processor cores is included in the first set of processor cores. ### Claim 21 (depends on 20) The one or more computer-readable storage media of claim 20, further comprising a plurality of instructions that in response to being executed cause the computing device to: re-assign any threads from the second set of processor cores to one or more processor cores of the computing device not in the second set of processor cores; bring the second set of processor cores into a low-power state in response to re-assigning any threads; notify the firmware interface with the second set of processor cores in response to bringing the second set of processor cores into the low-power state; and prevent interrupts to the second set of processor cores in response to bringing the second set of processor cores into the low-power state. ### Claim 22 (depends on 21) The one or more computer-readable storage media of claim 21, further comprising a plurality of instructions that in response to being executed cause the computing device to perform a platform management operation in response to notifying the firmware interface with the second set of processor cores. ### Claim 23 (depends on 22) The one or more computer-readable storage media of claim 22, wherein to perform the platform management operation comprises to enter, by each processor core of the second set of processor cores, a system management mode. ### Claim 24 (depends on 22) The one or more computer-readable storage media of claim 22, wherein to perform the platform management operation comprises to perform a specialized workload while the second set of processor cores are in the low-power state. ### Claim 25 (depends on 22) The one or more computer-readable storage media of claim 22, further comprising a plurality of instructions that in response to being executed cause the computing device to: notify, by the firmware interface of the computing device, an operating system of the computing device in response to performing the platform management operation to indicate that the platform management operation is completed; query the firmware interface to determine a third set of processor cores to bring online in response to notifying the operating system, wherein the third set of processor cores is included in the first set of processor cores; and bring the third set of processor cores into a normal power state.