# US 2017/0286323 A1 · Memory access protection apparatus and methods

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- Number: US 2017/0286323 A1
- Document ID: US20170286323A1
- Status: Published application
- Kind: A1
- Application number: 15/271,109
- Filed: 2016-09-20
- Published: 2017-10-05
- Earliest claimed: 2016-03-31
- Assignees: Apple Inc.
- Applicants: Apple Inc.
- Inventors: Saurabh Garg; Karan Sanghi; Vladislav Petkov; Haining Zhang
- Web page: https://patentgrep.com/patent/US20170286323A1

## CPC

- G06F 12/1441: {for a range}
- G06F 12/1081: for peripheral access to main memory, e.g. direct memory access [DMA]
- G06F 2212/1052: Security improvement
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Methods and apparatus for providing access to a shared memory resource. In one embodiment, a first processor generates a first window register associated with the shared memory resource; and transmits the first window register from the first processor to a second processor, the first window register defining a first extent of address space within the shared memory resource that is directly accessible by the second processor without requiring a performance of arbitration operations by the first processor.

## Claims

### Claim 1

A method for providing access to a shared memory resource, comprising:
generating, by a first processor, a first window register associated with the shared memory resource; and
transmitting the first window register from the first processor to a second processor, the first window register defining a first extent of address space within the shared memory resource that is directly accessible by the second processor.

### Claim 2 (depends on 1)

The method of claim 1, wherein the generation of the first window register comprises:
generating, by the first processor, a base address that corresponds to a starting location within the shared memory resource; and
generating, by the first processor, a window length that corresponds to the first extent of address space within the shared memory resource from the starting location within the shared memory resource.

### Claim 3 (depends on 2)

The method of claim 2, wherein the generation of the first window register comprises generating the first window register upon occurrence of a predefined event.

### Claim 4 (depends on 3)

The method of claim 3, wherein the predefined event comprises a second processor boot process.

### Claim 5 (depends on 3)

The method of claim 3, further comprising:
generating, by the first processor, a second window register associated with the shared memory resource; and
transmitting the second window register from the first processor to the second processor, the second window register defining a second extent of address space within the shared memory resource that is directly accessible by the second processor.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
responsive to an attempt to access an extent of address space outside of the extent of accessible address space, receiving a nullified packet transmitted by the second processor.

### Claim 7 (depends on 6)

The method of claim 6, wherein the reception of the nullified packet by the first processor, further comprises receiving an inverted data link layer cyclic redundancy check (LCRC) value for the nullified packet.

### Claim 8 (depends on 6)

The method of claim 6, wherein upon reception of the nullified packet by the first processor, disregarding the nullified packet.

### Claim 9

A computing device comprising a memory mapped system, the computing device comprising:
a host processing device comprising a host CPU and a host memory management unit (MMU);
a peripheral processing device comprising a peripheral CPU, a peripheral MMU, peripheral memory and a peripheral direct memory access (DMA) unit; and
a host memory accessible by both the host processing device and the peripheral processing device;
wherein the host processing device further comprises logic configured to:
generate a first window register associated with the host memory; and
transmit the first window register from the host processing device to the peripheral processing device, the first window register defining a first extent of address space within the host memory that is directly accessible by the peripheral processing device.

### Claim 10 (depends on 9)

The computing device of claim 9, wherein the host processing device further comprises logic configured to prevent access of the first extent of address space within the host memory by the host processing device.

### Claim 11 (depends on 9)

The computing device of claim 9, wherein the first window register is defined by the host processing device during a boot process for the memory mapped system.

### Claim 12 (depends on 9)

The computing device of claim 9, wherein the first window register comprises both: (1) a base address, and (2) a window length, the base address and the window length configured to define the first extent of address space within the host memory.

### Claim 13 (depends on 9)

The computing device of claim 9, wherein the memory mapped system further comprises a window configuration register, the window configuration register configured to be read and/or written by the host processing device and the peripheral processing device.

### Claim 14 (depends on 13)

The computing device of claim 13, wherein the window configuration register further comprises an available window field and the peripheral processing device is further configured to write a value into the available window field; and
wherein the host processing device is further configured to read the value in the available window field, the read value being utilized by the host processing device in order to determine whether the host processing device should write a value to a windows enabled field of the window configuration register.

### Claim 15 (depends on 14)

The computing device of claim 14, wherein the host processing device is further configured to write a default value to the windows enabled field of the window configuration register, the default value being indicative of a legacy peripheral processing device that is incompatible with support of the one or more window registers.

### Claim 16 (depends on 13)

The computing device of claim 13, wherein the host processing device is further configured to write to one or more locking bits of the window configuration register, the one or more locking bits configured to prevent the update of any fields located within one or more window registers.

### Claim 17

A peripheral processing device configured to access host memory within a memory mapped system, the peripheral processing device comprising:
a peripheral CPU, a peripheral MMU, peripheral memory and a peripheral direct memory access (DMA) unit and further comprising logic configured to:
receive a first window register from a host processing device, the first window register defining a first extent of address space within the host memory resource that is directly accessible by the peripheral processing device.

### Claim 18 (depends on 17)

The peripheral processing device of claim 17, further comprising logic configured to:
expose a capability register which the host processing device can access, the capability register comprising a windows enabled field and a windows available field.

### Claim 19 (depends on 18)

The peripheral processing device of claim 18, further comprising logic configured to:
write a first value into the windows available field, the first value comprising a maximum number of windows supported by the peripheral processing device.

### Claim 20 (depends on 19)

The peripheral processing device of claim 19, further comprising logic configured to:
read a second value from the windows enabled field, the second value indicating to the peripheral processing device a number of windows enabled by the host processing device.