# US 2017/0286302 A1 · Hardware apparatuses and methods for memory performance monitoring > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0286302 A1 - Document ID: US20170286302A1 - Status: Published application - Kind: A1 - Application number: 15/089,534 - Filed: 2016-04-02 - Published: 2017-10-05 - Earliest claimed: 2016-04-02 - Assignees: Intel Corporation - Inventors: Amitabha Roy; Subramanya R. Dulloor; Rajesh M. Sankaran - Web page: https://patentgrep.com/patent/US20170286302A1 ## CPC - G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means - G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] - G06F 2212/1044: Space efficiency improvement - G06F 2212/621: Coherency control relating to peripheral accessing, e.g. from DMA or I/O device - G06F 2212/68: Details of translation look-aside buffer [TLB] - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Methods and apparatuses relating to memory performance monitoring are described. In one embodiment, a processor includes at least one core, a performance monitoring unit, and a memory management unit including a first allocator to allocate a first virtual memory region of a memory for a first data structure, a second allocator to allocate a second, different virtual memory region of the memory for a second data structure, wherein the memory management unit is to, for each memory access request from the at least one core, set a monitor flag when a virtual address of a memory access request is in the first virtual memory region and set the monitor flag when the virtual address of the memory access request is in the second, different virtual memory region, and enable the performance monitoring unit to monitor the memory access request when the monitor flag is set. ## Claims ### Claim 1 A processor comprising: at least one core; a performance monitoring unit; and a memory management unit comprising a first allocator to allocate a first virtual memory region of a memory for a first data structure, a second allocator to allocate a second, different virtual memory region of the memory for a second data structure, wherein the memory management unit is to, for each memory access request from the at least one core, set a monitor flag when a virtual address of a memory access request is in the first virtual memory region and set the monitor flag when the virtual address of the memory access request is in the second, different virtual memory region, and enable the performance monitoring unit to monitor the memory access request when the monitor flag is set. ### Claim 2 (depends on 1) The processor of claim 1, wherein the memory management unit is to translate the virtual address of the memory access request to a physical address and append the monitor flag to the physical address when the virtual address is in either of the first virtual memory region and the second, different virtual memory region. ### Claim 3 (depends on 1) The processor of claim 1, further comprising a first lower bound register to set a lower bound of the first virtual memory region and a first upper bound register to set an upper bound of the first virtual memory region, wherein the memory management unit is to set the monitor flag for the virtual address of the memory access request that is one of between the lower bound and the upper bound, at the lower bound, and at the upper bound. ### Claim 4 (depends on 3) The processor of claim 3, further comprising a translation lookaside buffer (TLB), and wherein the TLB is to translate the virtual address of the memory access request to a physical address in parallel with a check by the memory management unit if the virtual address of the memory access request is one of between the lower bound and the upper bound, at the lower bound, and at the upper bound. ### Claim 5 (depends on 3) The processor of claim 3, wherein a second lower bound register and a second upper bound register are set to contain an empty range when a value in the second upper bound register is smaller than a value in the second lower bound register. ### Claim 6 (depends on 1) The processor of claim 1, further comprising a translation lookaside buffer (TLB) comprising a protection key for a page of a page table, and wherein the TLB is to translate the virtual address of the memory access request to a physical address and to set the monitor flag when the page includes the virtual address of the memory access request and the protection key indexes into a key register that indicates the virtual address of the memory access request is to be monitored. ### Claim 7 (depends on 1) The processor of claim 1, wherein the memory management unit is to save the monitor flag on a context switch. ### Claim 8 (depends on 1) The processor of claim 1, wherein the memory management unit is to enable the performance monitoring unit to monitor the memory access request for the virtual address when the monitor flag is set and the memory access request is to generate a performance monitoring event. ### Claim 9 A method comprising: allocating a first virtual memory region of a memory for a first data structure with a first allocator; allocating a second, different virtual memory region of the memory for a second data structure with a second allocator; detecting a memory access request to the memory; setting a monitor flag, for each memory access request, when a virtual address of a memory access request is in the first virtual memory region and when the virtual address of the memory access request is in the second, different virtual memory region; and enabling a performance monitoring unit to monitor the memory access request when the monitor flag is set. ### Claim 10 (depends on 9) The method of claim 9, further comprising: translating the virtual address of the memory access request to a physical address; and appending the monitor flag to the physical address when the virtual address is in either of the first virtual memory region and the second, different virtual memory region. ### Claim 11 (depends on 9) The method of claim 9, further comprising storing a lower bound value in a first lower bound register to set a lower bound of the first virtual memory region and an upper bound value in a first upper bound register to set an upper bound of the first virtual memory region, wherein the setting comprises setting the monitor flag for the virtual address of the memory access request that is one of between the lower bound and the upper bound, at the lower bound, and at the upper bound. ### Claim 12 (depends on 11) The method of claim 11, further comprising translating the virtual address of the memory access request to a physical address with a translation lookaside buffer (TLB) in parallel with checking if the virtual address of the memory access request is one of between the lower bound and the upper bound, at the lower bound, and at the upper bound. ### Claim 13 (depends on 11) The method of claim 11, further comprising setting a value in a second upper bound register to be smaller than a value in a second lower bound register to indicate an empty range. ### Claim 14 (depends on 9) The method of claim 9, further comprising: translating the virtual address of the memory access request to a physical address with a translation lookaside buffer (TLB) comprising a protection key for a page of a page table; and wherein the setting comprises setting the monitor flag when the page includes the virtual address of the memory access request and the protection key indexes into a key register that indicates the virtual address of the memory access request is to be monitored. ### Claim 15 (depends on 9) The method of claim 9, further comprising saving the monitor flag on a context switch. ### Claim 16 (depends on 9) The method of claim 9, wherein the enabling comprises enabling the performance monitoring unit to monitor the memory access request when the monitor flag is set and the memory access request is to generate a performance monitoring event. ### Claim 17 A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising: allocating a first virtual memory region of a memory for a first data structure with a first allocator; allocating a second, different virtual memory region of the memory for a second data structure with a second allocator; detecting a memory access request to the memory; setting a monitor flag, for each memory access request, when a virtual address of a memory access request is in the first virtual memory region and when the virtual address of the memory access request is in the second, different virtual memory region; and enabling a performance monitoring unit to monitor the memory access request when the monitor flag is set. ### Claim 18 (depends on 17) The non-transitory machine readable medium of claim 17, wherein the method further comprises: translating the virtual address of the memory access request to a physical address; and appending the monitor flag to the physical address when the virtual address is in either of the first virtual memory region and the second, different virtual memory region. ### Claim 19 (depends on 17) The non-transitory machine readable medium of claim 17, wherein the method further comprises storing a lower bound value in a first lower bound register to set a lower bound of the first virtual memory region and an upper bound value in a first upper bound register to set an upper bound of the first virtual memory region, wherein the setting comprises setting the monitor flag for the virtual address of the memory access request that is one of between the lower bound and the upper bound, at the lower bound, and at the upper bound. ### Claim 20 (depends on 19) The non-transitory machine readable medium of claim 19, wherein the method further comprises translating the virtual address of the memory access request to a physical address with a translation lookaside buffer (TLB) in parallel with checking if the virtual address of the memory access request is one of between the lower bound and the upper bound, at the lower bound, and at the upper bound. ### Claim 21 (depends on 19) The non-transitory machine readable medium of claim 19, wherein the method further comprises setting a value in a second upper bound register to be smaller than a value in a second lower bound register to indicate an empty range. ### Claim 22 (depends on 17) The non-transitory machine readable medium of claim 17, wherein the method further comprises: translating the virtual address of the memory access request to a physical address with a translation lookaside buffer (TLB) comprising a protection key for a page of a page table; and wherein the setting comprises setting the monitor flag when the page includes the virtual address of the memory access request and the protection key indexes into a key register that indicates the virtual address of the memory access request is to be monitored. ### Claim 23 (depends on 17) The non-transitory machine readable medium of claim 17, wherein the method further comprises saving the monitor flag on a context switch. ### Claim 24 (depends on 17) The non-transitory machine readable medium of claim 17, wherein the method further comprises enabling the performance monitoring unit to monitor the memory access request when the monitor flag is set and the memory access request is to generate a performance monitoring event.