# US 2017/0286295 A1 · Apparatus and method for triggered prefetching to improve i/o and producer-consumer workload efficiency > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0286295 A1 - Document ID: US20170286295A1 - Status: Published application - Kind: A1 - Application number: 15/089,035 - Filed: 2016-04-01 - Published: 2017-10-05 - Earliest claimed: 2016-04-01 - Assignees: Intel Corporation - Inventors: CHRISTOPHER B. WILERKSON; REN WANG; ANTOINE KAUFMANN; ANIL VASUDEVAN; ROBERT G. BLANKENSHIP; VENKATA KRISHNAN; TSUNG-YUAN C. TAI - Web page: https://patentgrep.com/patent/US20170286295A1 ## CPC - G06F 12/0808: with cache invalidating means (G06F12/0815 takes precedence) - G06F 12/0862: with prefetch - G06F 12/0891: using clearing, invalidating or resetting means - G06F 2212/1016: Performance improvement - G06F 2212/602: Details relating to cache prefetching - G06F 2212/6022: Using a prefetch buffer or dedicated prefetch cache - G06F 2212/6028: Prefetching based on hints or prefetch instructions - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus and method are described for a triggered prefetch operation. For example, one embodiment of a processor comprises: a first core comprising a first cache to store a first set of cache lines; a second core comprising a second cache to store a second set of cache lines; a cache management circuit to maintain coherency between one or more cache lines in the first cache and the second cache, the cache management circuit to allocate a lock on a first cache line to the first cache; a prefetch circuit comprising a prefetch request buffer to store a plurality of prefetch request entries including a first prefetch request entry associated with the first cache line, the prefetch circuit to cause the first cache line to be prefetched to the second cache in response to an invalidate command detected for the first cache line. ## Claims ### Claim 1 A processor comprising: a first core comprising a first cache to store a first set of cache lines; a second core comprising a second cache to store a second set of cache lines; a cache management circuit to maintain coherency between one or more cache lines in the first cache and the second cache, the cache management circuit to allocate a lock on a first cache line to the first cache; a prefetch circuit comprising a prefetch request buffer to store a plurality of prefetch request entries including a first prefetch request entry associated with the first cache line, the prefetch circuit to cause the first cache line to be prefetched to the second cache in response to an invalidate command detected for the first cache line. ### Claim 2 (depends on 1) The processor as in claim 1 further comprising: execution logic to execute a deferred prefetch instruction to cause the prefetch circuit to store the first prefetch request entry in the prefetch request buffer. ### Claim 3 (depends on 2) The processor as in claim 2 wherein the first prefetch request entry comprises an invalidate address associated with the first cache line, wherein an address associated with the invalidate command is to be compared with the invalidate address and, if a match is found, then the prefetch circuit to cause the first cache line to be prefetched to the second cache. ### Claim 4 (depends on 1) The processor as in claim 1 wherein the first core is to acquire a lock on the first cache line and modify the first cache line prior to the invalidate command being generated. ### Claim 5 (depends on 4) The processor as in claim 4 wherein the first core releases the lock upon completing modifications to the first cache line, the modifications to the first cache line causing the invalidate command to be generated to invalidate the first cache line in the second cache. ### Claim 6 (depends on 5) The processor as in claim 5 wherein the second core is to acquire the lock on the first cache line after receipt of the invalidate command. ### Claim 7 (depends on 1) The processor as in claim 1 wherein the first cache line is to be prefetched from a last level cache (LLC) or a system memory. ### Claim 8 A processor comprising: an I/O interface circuit to access a first set of cache lines in a first cache; a core comprising a second cache to store a second set of cache lines; a cache management circuit to maintain coherency between one or more cache lines in the first cache and the second cache, the cache management circuit to allocate a lock on a first cache line to the I/O interface circuit; a prefetch circuit comprising a prefetch request buffer to store a plurality of prefetch request entries including a first prefetch request entry associated with the first cache line, the prefetch circuit to cause the first cache line to be prefetched to the second cache in response to an invalidate command detected for the first cache line. ### Claim 9 (depends on 8) The processor as in claim 8 wherein the I/O interface circuit comprises a network interface controller (NIC) and wherein the first cache comprises a last level cache (LLC). ### Claim 10 (depends on 8) The processor as in claim 8 further comprising: execution logic to execute a deferred prefetch instruction to cause the prefetch circuit to store the first prefetch request entry in the prefetch request buffer. ### Claim 11 (depends on 10) The processor as in claim 10 wherein the first prefetch request entry comprises an invalidate address associated with the first cache line, wherein an address associated with the invalidate command is to be compared with the invalidate address and, if a match is found, then the prefetch circuit to cause the first cache line to be prefetched to the second cache. ### Claim 12 (depends on 8) The processor as in claim 8 wherein the I/O interface circuit is to acquire a lock on the first cache line and modify the first cache line prior to the invalidate command being generated. ### Claim 13 (depends on 12) The processor as in claim 12 wherein the first core releases the lock upon completing modifications to the first cache line, the modifications to the first cache line causing the invalidate command to be generated to invalidate the first cache line in the second cache. ### Claim 14 (depends on 13) The processor as in claim 13 wherein the second core is to acquire the lock on the first cache line after receipt of the invalidate command. ### Claim 15 (depends on 9) The processor as in claim 9 wherein the first cache line is to be prefetched from the LLC and stored in a mid-level cache (MLC) of the core. ### Claim 16 A system comprising: a memory to store instructions and data; a processor to execute the instructions and process the data; a graphics processor to perform graphics operations in response to graphics instructions; a network interface to receive and transmit data over a network; an interface for receiving user input from a mouse or cursor control device, the plurality of cores executing the instructions and processing the data responsive to the user input; the processor comprising: a first core comprising a first cache to store a first set of cache lines; a second core comprising a second cache to store a second set of cache lines; a cache management circuit to maintain coherency between one or more cache lines in the first cache and the second cache, the cache management circuit to allocate a lock on a first cache line to the first cache; a prefetch circuit comprising a prefetch request buffer to store a plurality of prefetch request entries including a first prefetch request entry associated with the first cache line, the prefetch circuit to cause the first cache line to be prefetched to the second cache in response to an invalidate command detected for the first cache line. ### Claim 17 (depends on 16) The system as in claim 16 further comprising: execution logic to execute a deferred prefetch instruction to cause the prefetch circuit to store the first prefetch request entry in the prefetch request buffer. ### Claim 18 (depends on 17) The system as in claim 17 wherein the first prefetch request entry comprises an invalidate address associated with the first cache line, wherein an address associated with the invalidate command is to be compared with the invalidate address and, if a match is found, then the prefetch circuit to cause the first cache line to be prefetched to the second cache. ### Claim 19 (depends on 16) The system as in claim 16 wherein the first core is to acquire a lock on the first cache line and modify the first cache line prior to the invalidate command being generated. ### Claim 20 (depends on 19) The system as in claim 19 wherein the first core releases the lock upon completing modifications to the first cache line, the modifications to the first cache line causing the invalidate command to be generated to invalidate the first cache line in the second cache. ### Claim 21 (depends on 20) The system as in claim 20 wherein the second core is to acquire the lock on the first cache line after receipt of the invalidate command. ### Claim 22 (depends on 16) The system as in claim 16 wherein the first cache line is to be prefetched from a last level cache (LLC) or a system memory.