# US 2017/0286293 A1 · Wear leveling based on a swapping operation between sets of physical block addresses of a non-volatile memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0286293 A1 - Document ID: US20170286293A1 - Status: Published application - Kind: A1 - Application number: 15/089,133 - Filed: 2016-04-01 - Published: 2017-10-05 - Earliest claimed: 2016-04-01 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Jason A. Gayman; Robert W. Faber - Web page: https://patentgrep.com/patent/US20170286293A1 ## CPC - G06F 12/0646: {Configuration or reconfiguration} - G06F 2212/7211: Wear leveling - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A first set representing a first plurality of physical block addresses of a non-volatile memory and a second set representing a second plurality of physical block addresses of the non-volatile memory may be identified. In response to a request to perform a wear leveling operation, first data from a first physical block address of the first set may be swapped with second data from a first physical block address of the second set. A second physical block address of the first set that is adjacent to the first physical block address of the first set may be identified. Third data from the second physical block address of the first set may be swapped with fourth data from a second physical block address of the second set that is adjacent to the first physical block of the second set. ## Claims ### Claim 1 An apparatus comprising: a non-volatile memory; and a controller, coupled to the non-volatile memory, to: identify a first set of a first plurality of physical block addresses of the non-volatile memory; identify a second set of a second plurality of physical block addresses of the non-volatile memory, a last physical block address of the first set being adjacent to a first physical block address of the second set; in response to a request to perform a wear leveling operation for the non-volatile memory, swap first data from a first physical block address of the first set with second data from the first physical block address of the second set; identify a second physical block address of the first set, the second physical block address of the first set being adjacent to the first physical block address of the first set; and swap third data from the second physical block address of the first set with fourth data from a second physical block address of the second set, the second physical block address of the second set being adjacent to the first physical block address of the second set. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the first plurality of physical block addresses and the second plurality of physical block addresses of the non-volatile memory are contiguous before the swapping of the first data from the first physical block address. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the first set is associated with a first number of write operations and the second set is associated with a second number of write operations, wherein the first number of write operations exceeds the second number of write operations, and wherein the first set corresponds to a memory region and the second set corresponds to a storage region. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the controller is further to: in response to the swap of the first data with the second data, update transform data associated with mapping a first logical address from the first physical block address of the first set to the first physical block address of the second set; and in response to the swap of the third data with the fourth data, update the transform data associated with mapping a second logical address from the second physical block address of the first set to the second physical block address of the second set. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the controller is further to: repeat for each subsequent physical block address of the first set after the second physical block address of the first set until data from each physical block address of the first set has been swapped with data from subsequent physical block addresses of the second set: increment a prior physical block address of the first set associated with data that was previously swapped with data of a prior physical block address of the second set to identify an incremented physical block address of the first set; and swap data from the incremented physical block address of the first set with data from a subsequent physical block address of the second set, the subsequent physical block address being adjacent to the prior physical block address of the second set. ### Claim 6 (depends on 1) The apparatus device of claim 1, wherein the swapping of the first data from the first physical block address is at a first time and the swapping of the third data from the second physical block address is at a second time after the first time. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the controller is further to: receive a read operation corresponding to a logical address; determine a particular physical block address corresponding to the logical address based on a transform in view of a start logical address of a span that includes the logical address and an offset for the span that includes the logical address; and retrieve particular data stored at the particular physical block address in response to the read operation. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the transform is implemented based on a comparator and a plurality of registers, wherein the plurality of registers identify the start logical address and the offset that identifies a corresponding physical block address to which the start logical address is mapped to. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the first set of the first plurality of physical block addresses corresponds to block addresses of a first non-volatile device of the non-volatile memory and the second set of the second plurality of physical block addresses corresponds to block addresses of a second non-volatile device of the non-volatile memory. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the non-volatile memory is a two-level memory that comprises a storage region and a memory region. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein a rate of the swapping is based on a rate of receiving write operations associated with the non-volatile memory. ### Claim 12 A method comprising identifying a first set of a first plurality of physical block addresses of a non-volatile memory; identifying a second set of a second plurality of physical block addresses of the non-volatile memory, a last physical block address of the first set being adjacent to a first physical block address of the second set; in response to a request to perform a wear leveling operation for the non-volatile memory, swapping, by a processing device, first data from a first physical block address of the first set with second data from the first physical block address of the second set; identifying a second physical block address , the second physical block address of the first set being adjacent to the first physical block address of the first set; and swapping third data from the second physical block address of the first set with fourth data from a second physical block address of the second set, the second physical block address of the second set being adjacent to the first physical block address of the second set. ### Claim 13 (depends on 12) The method of claim 12, wherein the first plurality of physical block addresses and the second plurality of physical block addresses of the non-volatile memory are contiguous before the swapping of the first data from the first physical block address. ### Claim 14 (depends on 12) The method of claim 12, wherein the first set is associated with a first number of write operations and the second set is associated with a second number of write operations, wherein the first number of write operations exceeds the second number of write operations, and wherein the first set corresponds to a memory region and the second set corresponds to a storage region. ### Claim 15 (depends on 12) The method of claim 12, further comprising: in response to the swap of the first data with the second data, updating transform data associated with mapping a first logical address from the first physical block address of the first set to the first physical block address of the second set; and in response to the swap of the third data with the fourth data, updating the transform data associated with mapping a second logical address from the second physical block address of the first set to the second physical block address of the second set. ### Claim 16 (depends on 12) The method of claim 12, further comprising: repeating for each subsequent physical block address of the first set after the second physical block address of the first set until data from each physical block address of the first set has been swapped with data from subsequent physical block addresses of the second set: incrementing a prior physical block address of the first set associated with data that was previously swapped with data of a prior physical block address of the second set to identify an incremented physical block address of the first set; and swapping data from the incremented physical block address of the first set with data from a subsequent physical block address of the second set, the subsequent physical block address being adjacent to the prior physical block address of the second set. ### Claim 17 (depends on 12) The method of claim 12, wherein the swapping of the first data from the first physical block address is at a first time and the swapping of the third data from the second physical block address is at a second time after the first time. ### Claim 18 (depends on 12) The method of claim 12, further comprising: receiving a read operation corresponding to a logical address; determining a particular physical block address corresponding to the logical address based on a transform in view of a start logical address of a span that includes the logical address and an offset for the span that includes the logical address; and retrieving particular data stored at the particular physical block address in response to the read operation. ### Claim 19 (depends on 18) The method of claim 18, wherein the transform is implemented based on a comparator and a plurality of registers, wherein the plurality of registers identify the start logical address and the offset that identifies a corresponding physical block address to which the start logical address is mapped to. ### Claim 20 An integrated circuit comprising: a solid-state drive (SSD) controller, coupled with a plurality of non-volatile memory devices associated with an address space of an SSD, to: identify a first set of a first plurality of locations of the address space of the SSD and a second set of a second plurality of locations of the address space of the SSD, a last location of the first set being adjacent to a first location of the second set; receive a request to perform a wear leveling operation for the SSD; in response to the request, swap first data from a first location of the first set with second data from the first location of the second set; identify a second location of the first set, the second location of the first set being adjacent to the first location of the first set; and swap third data from the second location of the first set with fourth data from a second location of the second set, the second location of the second set being adjacent to the first location of the second set. ### Claim 21 (depends on 20) The integrated circuit of claim 20, wherein the first plurality of locations of the address space and the second plurality of locations of the address space are contiguous before the swapping of the first data from the first location. ### Claim 22 (depends on 20) The integrated circuit of claim 20, wherein the first set is associated with a first number of write operations and the second set is associated with a second number of write operations, wherein the first number of write operations exceeds the second number of write operations, and wherein the first set corresponds to a memory region and the second set corresponds to a storage region. ### Claim 23 (depends on 20) The integrated circuit of claim 20, wherein the SSD controller is further to: in response to the swap of the first data from the first location with the second data, update transform data associated with mapping a first logical address from the first location of the first set to the first location of the second set; and in response to the swap of the third data from the second location with the fourth data, update the transform data associated with mapping a second logical address from the second location of the first set to the second location of the second set. ### Claim 24 (depends on 20) The integrated circuit of claim 20, wherein the SSD controller is further to: repeat for each subsequent location of the first set after the second location of the first set until data from each location of the first set has been swapped with data from subsequent locations of the second set: increment a prior location of the first set associated with data that was previously swapped with data of a prior location of the second set to identify an incremented location of the first set; and swap data from the incremented location of the first set with data from a subsequent location of the second set, the subsequent location being adjacent to the prior location of the second set. ### Claim 25 (depends on 20) The integrated circuit of claim 20, wherein the swapping of the first data from the first location is at a first time and the swapping of the third data from the second location is at a second time after the first time. ### Claim 26 (depends on 20) The integrated circuit of claim 20, wherein the SSD controller is further to: receive a read operation corresponding to a logical address; determine a particular physical block address corresponding to the logical address based on a transform in view of a start logical address of a span that includes the logical address and an offset for the span that includes the logical address; and retrieve particular data stored at the particular location in response to the read operation. ### Claim 27 (depends on 26) The integrated circuit of claim 26, wherein the transform is implemented based on a comparator and a plurality of registers, wherein the plurality of registers identify the start logical address and the offset that identifies a corresponding physical block address to which the start logical address is mapped to.