# US 2017/0286247 A1 · Apparatus and method for a scalable test engine

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- Number: US 2017/0286247 A1
- Document ID: US20170286247A1
- Status: Published application
- Kind: A1
- Application number: 15/089,448
- Filed: 2016-04-01
- Published: 2017-10-05
- Earliest claimed: 2016-04-01
- Assignees: Intel Corporation
- Inventors: LAKSHMINARAYANA PAPPU; ROBERT DE GRUIJL; SUKETU U. BHATT; ROBERT P. ADLER; R SELVAKUMAR RAJA GOPAL; RIUS TANADI
- Web page: https://patentgrep.com/patent/US20170286247A1

## CPC

- G06F 11/2736: {using a dedicated service processor for test}
- G01R 31/31915: {In-circuit Testers}
- G06F 30/30: Circuit design
- G06F 30/333: Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
- G06F 2115/08: Intellectual property [IP] blocks or IP cores
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

An apparatus and method are described for a scalable testing agent. For example, one embodiment of a scalable test engine comprises: an input interface to receive commands and/or data from a processor core or an external test system, the commands and/or data to specify one or more test operations to be performed on one or more intellectual property (IP) blocks of a chip; a first circuit to establish communication with an IP block over an interconnect fabric, the first circuit to transmit the one or more test operations to the IP block responsive to the received commands and/or data, the IP block to process the test operations and generate results; and a second circuit to receive the results from the IP block over the interconnect fabric, the results to be provided from the second circuit to the processor core and/or the external test system for analysis.

## Claims

### Claim 1

A scalable test engine comprising:
an input interface to receive commands and/or data from a processor core or an external test system, the commands and/or data to specify one or more test operations to be performed on one or more intellectual property (IP) blocks of a chip;
a first circuit to establish communication with an IP block over an interconnect fabric, the first circuit to transmit the one or more test operations to the IP block responsive to the received commands and/or data, the IP block to process the test operations and generate results; and
a second circuit to receive the results from the IP block over the interconnect fabric, the results to be provided from the second circuit to the processor core and/or the external test system for analysis.

### Claim 2 (depends on 1)

The scalable test engine as in claim 1 wherein the first circuit includes a first interconnect fabric interface to communicatively couple the first circuit to a the interconnect fabric to which the IP block is also communicatively coupled.

### Claim 3 (depends on 2)

The scalable test engine as in claim 2 wherein the interconnect fabric comprises a primary scalable fabric (PSF) for interconnecting IP blocks within a semiconductor chip.

### Claim 4 (depends on 3)

The scalable test engine as in claim 3 wherein the PSF comprises an Intel On-Chip System Fabric (IOSF).

### Claim 5 (depends on 2)

The scalable test engine as in claim 2 wherein the first circuit is to implement a first finite state machine to coordinate communication of the commands and/or data over the first interconnect fabric to the IP block.

### Claim 6 (depends on 5)

The scalable test engine as in claim 5 wherein the first circuit further comprises:
a plurality of command/data buffers, one or more of the command/data buffers to store a particular type of command/data received over the input interface.

### Claim 7 (depends on 6)

The scalable test engine as in claim 6 wherein a first command/data buffer is to store posted commands/data, a second command/data buffer is to store non-posted commands/data, and a third command/data buffer is to store completed commands/data.

### Claim 8 (depends on 1)

The scalable test engine as in claim 1 further comprising a data generation circuit to generate data to be transmitted to the IP block in combination with a command from one of the command/data buffers under control by the first FSM.

### Claim 9 (depends on 1)

The scalable test engine as in claim 1 wherein the results comprise one or more signatures generated at the IP block responsive to execution of the test operations, the IP block to transmit the one or more signatures to the second circuit over the interconnect fabric.

### Claim 10 (depends on 9)

The scalable test engine as in claim 9 wherein the signatures are to be compared against known good signatures to determine whether the IP block has passed the test operations.

### Claim 11 (depends on 1)

The scalable test engine as in claim 1 wherein the interconnect fabric is communicatively coupled to a memory controller to establish communication between a system memory and the first and second circuits.

### Claim 12 (depends on 1)

The scalable test engine as in claim 1 wherein the input interface comprises a sideband interface communicatively coupling the first and second circuits to the processor core.

### Claim 13 (depends on 1)

The scalable test engine as in claim 1 further comprising:
an on-chip test access port (TAP) to implement a stateful protocol in accordance with a Joint Test Action Group (JTAG) standard.

### Claim 14 (depends on 1)

The scalable test engine as in claim 1 wherein the second circuit comprises a plurality of multi-input serial registers (MISRs) to be updated with the results under control of a target finite state machine (FSM).

### Claim 15

A system-on-a-chip (SoC) comprising:
a plurality of intellectual property (IP) blocks interconnected on an interconnect fabric;
at least one processor core to execute instructions and process data;
an input interface to receive commands and/or data from the processor core or an external test system, the commands and/or data to specify one or more test operations to be performed on one or more IP blocks of a chip;
a first circuit to establish communication with an IP block over the interconnect fabric, the first circuit to transmit the one or more test operations to the IP block responsive to the received commands and/or data, the IP block to process the test operations and generate results; and
a second circuit to receive the results from the IP block over the interconnect fabric, the results to be provided from the second circuit to the processor core and/or the external test system for analysis.

### Claim 16 (depends on 15)

The SoC as in claim 15 wherein the first circuit includes a first interconnect fabric interface to communicatively couple the first circuit to a the interconnect fabric to which the IP block is also communicatively coupled.

### Claim 17 (depends on 16)

The SoC as in claim 16 wherein the interconnect fabric comprises a primary scalable fabric (PSF) for interconnecting IP blocks within a semiconductor chip.

### Claim 18 (depends on 17)

The SoC as in claim 17 wherein the PSF comprises an Intel On-Chip System Fabric (IOSF).

### Claim 19 (depends on 16)

The SoC as in claim 16 wherein the first circuit is to implement a first finite state machine to coordinate communication of the commands and/or data over the first interconnect fabric to the IP block.

### Claim 20 (depends on 19)

The SoC as in claim 19 wherein the first circuit further comprises:
a plurality of command/data buffers, one or more of the command/data buffers to store a particular type of command/data received over the input interface.

### Claim 21 (depends on 20)

The SoC as in claim 20 wherein a first command/data buffer is to store posted commands/data, a second command/data buffer is to store non-posted commands/data, and a third command/data buffer is to store completed commands/data.

### Claim 22 (depends on 15)

The SoC as in claim 15 further comprising a data generation circuit to generate data to be transmitted to the IP block in combination with a command from one of the command/data buffers under control by the first FSM.

### Claim 23 (depends on 15)

The SoC as in claim 15 wherein the results comprise one or more signatures generated at the IP block responsive to execution of the test operations, the IP block to transmit the one or more signatures to the second circuit over the interconnect fabric.

### Claim 24 (depends on 23)

The SoC as in claim 23 wherein the signatures are to be compared against known good signatures to determine whether the IP block has passed the test operations.

### Claim 25 (depends on 15)

The SoC as in claim 15 wherein the interconnect fabric is communicatively coupled to a memory controller to establish communication between a system memory and the first and second circuits.