# US 2017/0286240 A1 · Resiliency to memory failures in computer systems

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- Number: US 2017/0286240 A1
- Document ID: US20170286240A1
- Status: Published application
- Kind: A1
- Application number: 15/625,957
- Filed: 2017-06-16
- Published: 2017-10-05
- Earliest claimed: 2012-05-21
- Assignees: Cray Inc.
- Applicants: Cray Inc.
- Inventors: Laurence S. Kaplan; Preston Pengra Briggs Ill; Miles Arthur Ohlrich; Willard Huston Leslie
- Web page: https://patentgrep.com/patent/US20170286240A1

## CPC

- G06F 11/1076: {Parity data used in redundant arrays of independent storages, e.g. in RAID systems}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/064: {Management of blocks}
- G06F 3/067: {Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]}
- G06F 3/0673: {Single storage device}
- G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)}
- G06F 11/1088: {Reconstruction on already foreseen single or plurality of spare disks}
- G06F 11/141: {for bus or memory accesses}
- G06F 11/1662: {the resynchronized component or unit being a persistent storage device (re-synchronization of failed mirror storage G06F11/2082; rebuild or reconstruction of parity RAID storage G06F11/1008)}
- G06F 11/2023: {Failover techniques}
- G06F 11/08: Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F 11/10: Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F 11/1008: {in individual solid state devices (G06F11/1004 takes precedence)}
- G06F 11/1016: {Error in accessing a memory location, i.e. addressing error}
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G06F 11/14: Error detection or correction of the data by redundancy in operations (error detection or correction of the data by redundancy in hardware G06F11/16)
- G06F 11/1402: {Saving, restoring, recovering or retrying}
- G06F 11/1405: {at machine instruction level}
- G06F 11/1479: Generic software techniques for error detection or fault masking
- G06F 11/202: {where processing functionality is redundant (redundant communication control functionality G06F11/2005, redundant storage control functionality G06F11/2089)}
- G06F 11/2035: {without idle spare hardware}
- G06F 2201/805: Real-time
- G06F 2201/82: Solving problems relating to consistency
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.

## Claims

### Claim 1

A method performed by a computing system for reconstructing a resilient segment of a network of nodes with a distributed memory, a first node of the network of nodes hosting a portion of the resilient segment, the method comprising:
when a replacement node is to replace the first node, for each data word of the portion of the resilient segment,
collecting by the replacement node from nodes other than the first node error correction information sufficient to re-create that data word;
re-creating that data word based on the collected error correction information; and
storing the re-created data word in a replacement portion of the resilient segment of the replacement node.

### Claim 2 (depends on 1)

The method of claim 1 further comprising, for each check word stored in memory of the first node, re-creating and storing by the replacement node that check word.

### Claim 3 (depends on 1)

The method of claim 1 wherein that data word is a data word of a check unit and the error correction information includes the other data words of the check unit and a check word for the check unit.

### Claim 4 (depends on 1)

The method of claim 1 wherein each of the replacement node and the nodes other than the first node stores only one data word of a check unit.

### Claim 5 (depends on 1)

The method of claim 1 wherein the replacement node detects that the first node fails.

### Claim 6 (depends on 1)

The method of claim 1 further comprising notifying the nodes of the network that the replacement node has replaced the first node.

### Claim 7 (depends on 1)

The method of claim 1 wherein the first node is to be replaced when the first node fails.

### Claim 8 (depends on 1)

The method of claim 1 wherein when another node receives a memory error when attempting to load a data word of the portion of the resilient segment, the other node independently re-creates the data word from error correction information stored at nodes other than the first node.

### Claim 9 (depends on 1)

The method of claim 1 wherein the data words of the resilient segment are organized into check units with each check unit have a check word such that when a memory error is occurs when loading a data word from a check unit, re-creating that data word using the other data words of the check unit and the check word.

### Claim 10

A computing system for reconstructing a portion of a resilient segment, the portion being stored at a first node of a network of nodes with a distributed memory, the computing system comprising:
one or more computer-readable storage mediums storing computer-executable instructions for controlling the computing system to, when a replacement node is to replace the first node, for each data word of the portion of the resilient segment:
collect, from nodes other than the first node, error correction information sufficient to re-create that data word;
re-create that data word based on the collected error correction information; and
store the re-created data word in memory of the replacement node as a replacement portion of the resilient segment; and
one or more processor for executing the computer-executable instructions stored in the one or more computer-readable storage mediums.

### Claim 11 (depends on 10)

The computing system of claim 10 wherein the computer-executable instructions further control the computing system to, for each check word stored in memory of the first node, re-create and store that check word in memory of the replacement node.

### Claim 12 (depends on 10)

The computing system of claim 10 wherein that data word is a data word of a check unit and the error correction information includes the other data words of the check unit and a check word for the check unit.

### Claim 13 (depends on 10)

The computing system of claim 10 wherein each of the replacement node and the nodes other than the first node store only one data word of a check unit.

### Claim 14 (depends on 10)

The computing system of claim 10 wherein the replacement node detects when the first node fails.

### Claim 15 (depends on 10)

The computing system of claim 10 wherein the computing system is the replacement node.

### Claim 16

A method performed by a computing system for providing resiliency to memory of an application program, the method comprising:
when storing a data word in the memory,
generating error correction information for the data word;
storing the generated error correction information in association with the data word; and
storing the data word in the memory; and
when a memory error occurs during executing of a load instruction to load the data word from the memory,
re-creating the data word based on error correction information associated with data word; and
providing the re-created data word as a result of the execution of the load instruction.

### Claim 17 (depends on 16)

The method of claim 16 further comprising:
receiving from the application program a request to register a segment of the memory to be resilient; and
receiving from the application a request to register a re-create data word component to perform the re-creating of the data word.

### Claim 18 (depends on 16)

The method of claim 16 wherein resiliency is provided to a resilient segment of memory and wherein the resilient segment includes the data words and is associated with a check word for each check unit of data words.

### Claim 19 (depends on 18)

The method of claim 18 wherein the error correction information includes the data words of a check unit and the check word associated with that check unit.

### Claim 20 (depends on 18)

The method of claim 18 wherein the resilient segment is stored in memory that is distributed across nodes and when a first node is to be replaced, re-creating data words stored in memory of the first node and storing the re-created data words in memory of a replacement node.