# US 2017/0286183 A1 · Operation of a multi-slice processor implementing a hardware level transfer of an execution thread > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0286183 A1 - Document ID: US20170286183A1 - Status: Published application - Kind: A1 - Application number: 15/086,835 - Filed: 2016-03-31 - Published: 2017-10-05 - Earliest claimed: 2016-03-31 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: BRIAN D. BARRICK; JAMES W. BISHOP; MARCY E. BYERS; SUNDEEP CHADHA; CLIFF KUCHARSKI; DUNG Q. NGUYEN; DAVID R. TERRY; JING ZHANG - Web page: https://patentgrep.com/patent/US20170286183A1 ## CPC - G06F 9/52: Program synchronisation; Mutual exclusion, e.g. by means of semaphores - G06F 9/3009: {Thread control instructions} - G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution} - G06F 9/461: {Saving or restoring of program or task context} - G06F 9/4856: {resumption being on a different machine, e.g. task migration, virtual machine migration (G06F9/5088 takes precedence)} - G06F 12/0875: with dedicated cache, e.g. instruction or stack - G06F 2212/452: Instruction code - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Operation of a multi-slice processor that includes execution slices and a dispatch network of the multi-slice processor implementing a hardware level transfer of an execution thread between execution slices. Operation of such a multi-slice processor includes responsive to a thread switch signal: halting dispatch of one or more instructions retrieved from an instruction cache; generating a plurality of instructions to transfer an execution thread from a first execution slice to a second execution slice; and dispatching the plurality of instructions instead of the one or more instructions retrieved from the instruction cache; and transferring, in dependence upon execution of the plurality of instructions from the thread switching instruction generator, the execution thread from the first execution slice to the second execution slice. ## Claims ### Claim 1 A method of operation of a multi-slice processor, the multi-slice processor including a plurality of execution slices, the method comprising: responsive to a thread switch signal: halting dispatch of one or more instructions retrieved from an instruction cache; generating a plurality of instructions to transfer an execution thread from a first execution slice to a second execution slice; and dispatching the plurality of instructions instead of the one or more instructions retrieved from the instruction cache; and transferring, in dependence upon executing the plurality of instructions, the execution thread from the first execution slice to the second execution slice. ### Claim 2 (depends on 1) The method of claim 1, further comprising: resuming dispatch of the one or more instructions retrieved from the instruction cache. ### Claim 3 (depends on 1) The method of claim 1, further comprising: propagating, by a hardware unit of the multi-slice processor, the plurality of instructions to a first multiplexer input of a multiplexer that supplies inputs to dispatch logic. ### Claim 4 (depends on 3) The method of claim 3, wherein a second multiplexer input of the multiplexer is provided with the one or more instructions received from the instruction cache, and wherein the multiplexer switches between the first multiplexer input and the second multiplexer input in dependence upon the thread switch signal. ### Claim 5 (depends on 4) The method of claim 4, wherein the dispatching the plurality of instructions instead of the one or more instructions retrieved from the instruction cache is in dependence upon the thread switch signal causing the multiplexer to provide the plurality of instructions as output. ### Claim 6 (depends on 1) The method of claim 1, wherein the plurality of instructions bypass an instruction issue queue and do not write into a completion table. ### Claim 7 (depends on 1) The method of claim 1, wherein the plurality of instructions comprise instructions for transferring general purpose register values from general purpose registers of the first execution slice to corresponding general purpose registers of the second execution slice. ### Claim 8 A multi-slice processor comprising: a plurality of execution slices, wherein the multi-slice processor is configured to carry out the steps of: responsive to a thread switch signal: halting dispatch of one or more instructions retrieved from an instruction cache; generating a plurality of instructions to transfer an execution thread from a first execution slice to a second execution slice; and dispatching the plurality of instructions instead of the one or more instructions retrieved from the instruction cache; and transferring, in dependence upon executing the plurality of instructions, the execution thread from the first execution slice to the second execution slice. ### Claim 9 (depends on 8) The multi-slice processor of claim 8, wherein the multi-slice processor is further configured to carry out the steps of: resuming dispatch of the one or more instructions retrieved from the instruction cache. ### Claim 10 (depends on 8) The multi-slice processor of claim 8, wherein the multi-slice processor is further configured to carry out the steps of: propagating, by a hardware unit of the multi-slice processor, the plurality of instructions to a first multiplexer input of a multiplexer that supplies inputs to dispatch logic. ### Claim 11 (depends on 10) The multi-slice processor of claim 10, wherein a second multiplexer input of the multiplexer is provided with the one or more instructions received from the instruction cache, and wherein the multiplexer switches between the first multiplexer input and the second multiplexer input in dependence upon the thread switch signal. ### Claim 12 (depends on 11) The multi-slice processor of claim 11, wherein the dispatching the plurality of instructions instead of the one or more instructions retrieved from the instruction cache is in dependence upon the thread switch signal causing the multiplexer to provide the plurality of instructions as output. ### Claim 13 (depends on 10) The multi-slice processor of claim 10, wherein the plurality of instructions bypass an instruction issue queue and do not write into a completion table. ### Claim 14 (depends on 8) The multi-slice processor of claim 8 wherein the plurality of instructions comprise instructions for transferring general purpose register values from general purpose registers of the first execution slice to corresponding general purpose registers of the second execution slice. ### Claim 15 An apparatus comprising: a multi-slice processor that includes a plurality of execution slices; and a computer memory operatively coupled to the multi-slice processor, wherein the multi-slice processor is configured to carry out the steps of: responsive to a thread switch signal: halting dispatch of one or more instructions retrieved from an instruction cache; generating a plurality of instructions to transfer an execution thread from a first execution slice to a second execution slice; and dispatching the plurality of instructions instead of the one or more instructions retrieved from the instruction cache; and transferring, in dependence upon executing the plurality of instructions, the execution thread from the first execution slice to the second execution slice. ### Claim 16 (depends on 15) The apparatus of claim 15, wherein the multi-slice processor if further configured to carry out the steps of: resuming dispatch of the one or more instructions retrieved from the instruction cache. ### Claim 17 (depends on 15) The apparatus of claim 15, wherein the multi-slice processor if further configured to carry out the steps of: propagating, by a hardware unit of the multi-slice processor, the plurality of instructions to a first multiplexer input of a multiplexer that supplies inputs to dispatch logic. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein a second multiplexer input of the multiplexer is provided with the one or more instructions received from the instruction cache, and wherein the multiplexer switches between the first multiplexer input and the second multiplexer input in dependence upon the thread switch signal. ### Claim 19 (depends on 18) The apparatus of claim 18, wherein the dispatching the plurality of instructions instead of the one or more instructions retrieved from the instruction cache is in dependence upon the thread switch signal causing the multiplexer to provide the plurality of instructions as output. ### Claim 20 (depends on 15) The apparatus of claim 15, wherein the plurality of instructions bypass an instruction issue queue and do not write into a completion table.