# US 2017/0286169 A1 · Automatically Mapping Program Functions to Distributed Heterogeneous Platforms Based on Hardware Attributes and Specified Constraints > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0286169 A1 - Document ID: US20170286169A1 - Status: Published application - Kind: A1 - Application number: 15/470,374 - Filed: 2017-03-27 - Published: 2017-10-05 - Earliest claimed: 2016-03-31 - Assignees: National Instruments Corporation - Applicants: National Instruments Corporation - Inventors: Kaushik Ravindran; Hugo A. Andrade; Ankita Prasad; Arkadeb Ghosal; Trung N. Tran; Rhishikesh Limaye; Patricia Derler; Jacob Kornerup - Web page: https://patentgrep.com/patent/US20170286169A1 ## CPC - G06F 9/5011: {the resources being hardware resources other than CPUs, Servers and Terminals} - G06F 9/5066: {Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs (mappping at compile time, see G06F8/451)} - G06F 13/366: using a centralised polling arbiter - G06F 13/4068: {Electrical coupling} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method for automatically mapping program functions to distributed heterogeneous platforms based on hardware attributes and specified constraints is disclosed. The method includes receiving a plurality of program functions and determining constraint information for each. The method further includes determining attributes of a plurality of hardware processing elements, wherein ones of the plurality of hardware processing elements have different attributes with respect to other ones of the hardware processing elements. The plurality of program functions may be automatically mapped for execution on at least a subset of the hardware processing elements, wherein the mapping is based on constraint information and the attributes. ## Claims ### Claim 1 A method, comprising: creating a program diagram in response to user input, wherein the program diagram comprises a plurality of interconnected icons that visually illustrate functionality of a program; creating a system diagram in response to user input, wherein the system diagram comprises a plurality of interconnected icons that visually illustrate a target system, wherein the target system comprises a plurality of heterogeneous hardware elements; determining, by the computer system, attributes of the plurality of heterogeneous hardware elements, wherein particular ones of the plurality of the heterogeneous hardware elements have different attributes with respect to other ones of the plurality of heterogeneous hardware elements; storing constraint information in a constraints file, wherein the constraint information includes information specifying constraints associated with particular ones of a plurality of program functions and further includes constraints associated with particular ones of the plurality of the heterogeneous hardware processing elements; and automatically generating a mapping, using a computer system, of selected portions of the program diagram for execution on correspondingly selected ones of the plurality of heterogeneous hardware elements, wherein the mapping is based on the constraint information and the attributes. ### Claim 2 (depends on 1) The method as recited in claim 1, automatically generating a mapping comprises a mapper engine reading information from an application graph comprising information pertaining to the program diagram, information from the constraints file, and information from a platform graph pertaining to a hardware platform in which the plurality of heterogeneous hardware elements are implemented. ### Claim 3 (depends on 1) The method as recited in claim 1, further comprising: the computer system simulating execution of behavior of the plurality of program functions independent of any hardware bindings; the computer system simulating execution of the selected ones of the plurality of program functions on the correspondingly selected ones of the plurality of heterogeneous hardware elements; and the computer system verifying correctness of operation of the selected ones of the plurality of program functions on the correspondingly selected ones of the plurality of hardware processing elements. ### Claim 4 (depends on 1) The method as recited in claim 1, further comprising the computer system automatically deploying the selected ones of the plurality of program functions for execution on the selected ones of the plurality of hardware processing elements, responsive to said mapping. ### Claim 5 (depends on 1) The method as recited in claim 1, further comprising the computer system providing feedback on the quality, performance, power, and other characteristics, from the deployed execution or simulated execution of the said mapping, and subsequently guiding design exploration by suggesting alternate mappings. ### Claim 6 (depends on 1) The method as recited in claim 1, further comprising the computer system enabling debugging of the behavior of program functions, from the deployed execution or simulated execution of said mapping. ### Claim 7 (depends on 1) The method as recited in claim 1, wherein the attributes of various ones of the plurality of hardware processing elements include one or more of the following: number of slices, number of processing elements, number of registers, amount of memory, available bandwidth, number of communication channels, parallel processing capability, or clock frequency, and wherein the plurality of hardware processing elements include one or more interconnects between computing devices. ### Claim 8 (depends on 1) The method as recited in claim 1, wherein constraint information associated various ones of the plurality of program functions include one or more of the following: a throughput constraint, frequency constraint, a timing constraint, an area constraint, an execution time constraint, or a memory requirement constraint. ### Claim 9 (depends on 1) The method as recited in claim 1, wherein the constraint information for at least first and second program functions of the plurality of functions includes exclusion information indicating that the first and second program functions are to be mapped to different hardware processing elements with respect to one another. ### Claim 10 (depends on 1) The method as recited in claim 1, wherein the constraint information for at least first and second program functions of the plurality of functions includes grouping information indicating that the first and second program functions are to be mapped to the same hardware processing element. ### Claim 11 (depends on 1) The method as recited in claim 1, wherein the constraint information includes affinity information indicating that a program function is to be mapped to a particular type of hardware processing element. ### Claim 12 (depends on 1) The method as recited in claim 1, wherein the plurality of program functions comprise a general multi-rate data flow program. ### Claim 13 A system comprising: a plurality of hardware processing elements; at least one processor; and a storage device storing a plurality of program functions, information pertaining to the plurality of hardware elements, and instructions that, when executed by the at least one processor, cause the at least one processor to: determine constraint information associated with the plurality of program functions; determine attributes of the plurality of hardware processing elements, wherein particular ones of the plurality of hardware processing elements have different attributes with respect to other ones of the plurality of hardware processing elements; and automatically generate a mapping of selected ones of the plurality of program functions for execution on correspondingly selected ones of the plurality of hardware processing elements, wherein the mapping is based on the constraint information and the attributes. ### Claim 14 (depends on 13) The system as recited in claim 13, wherein the computer system is further configured to simulate execution of the selected ones of the plurality of program functions on the correspondingly selected ones of the plurality of hardware processing elements. ### Claim 15 (depends on 13) The system as recited in claim 13, wherein the computer system is further configured to verify correctness of operation of the selected ones of the plurality of program functions on the correspondingly selected ones of the plurality of hardware processing elements. ### Claim 16 (depends on 13) The system as recited in claim 13, wherein the attributes of various ones of the plurality of hardware processing elements include one or more of the following: number of slices, number of processing elements, number of registers, amount of memory, available bandwidth, number of communication channels, parallel processing capability, or clock frequency. ### Claim 17 (depends on 13) The system as recited in claim 13, wherein constraint information associated various ones of the plurality of program functions include one or more of the following: a throughput constraint, frequency constraint, a timing constraint, an area constraint, an execution time constraint, or a memory requirement constraint ### Claim 18 (depends on 13) The system as recited in claim 13, wherein the constraint information includes: exclusion information indicative of particular ones of the plurality of program functions that are to be mapped to different hardware processing elements with respect to one or more other ones of the plurality of program functions; grouping information indicative of particular ones of the plurality of program functions that are to be mapped to a same hardware processing element as one or more other ones of the plurality of program functions; and affinity information indicative of a particular type of hardware processing element to which a particular one of the plurality of program functions is to be mapped. ### Claim 19 (depends on 13) The system as recited in claim 13, wherein the computer system is configured to automatically generate the mapping without prompting a user for additional input. ### Claim 20 A non-transitory computer readable medium storing instructions that, when executed by a computer system, cause the computer system to perform the following: determine constraint information associated with the plurality of program functions; determine attributes of the plurality of hardware processing elements, wherein particular ones of the plurality of hardware processing elements have different attributes with respect to other ones of the plurality of hardware processing elements; and automatically generate a mapping, using a computer system, of selected ones of the plurality of program functions for execution on correspondingly selected ones of the plurality of hardware processing elements, wherein the mapping is based on the constraint information and the attributes.