# US 2017/0286122 A1 · Instruction, Circuits, and Logic for Graph Analytics Acceleration

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- Number: US 2017/0286122 A1
- Document ID: US20170286122A1
- Status: Published application
- Kind: A1
- Application number: 15/089,232
- Filed: 2016-04-01
- Published: 2017-10-05
- Earliest claimed: 2016-04-01
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Lisa K. Wu; Tae Jun Ham; Nadathur Rajagopalan Satish; Narayanan Sundaram
- Web page: https://patentgrep.com/patent/US20170286122A1

## CPC

- G06F 9/5027: {the resource being a machine, e.g. CPUs, Servers, Terminals}
- G06F 9/3877: {using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12)}
- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06F 2209/509: Offload
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A processor includes a front end including circuitry to receive and decode an instruction. The instruction is to perform a graph analytic function and pass the instruction to a graph accelerator. The graph accelerator including circuitry to process graph vertices and graph edges as datatypes, execute the instruction, and pass results of the instruction to a memory subsystem of the processor.

## Claims

### Claim 1

A processor, comprising:
a front end including circuitry to:
receive and decode an instruction, the instruction to perform a graph analytic function; and
pass the instruction to a graph accelerator;
a graph accelerator including circuitry to:
process graph vertices and graph edges as datatypes;
execute the instruction;
pass results of the instruction to a memory subsystem of the processor.

### Claim 2 (depends on 1)

The processor of claim 1, wherein the graph accelerator further includes circuitry to stream inputs of vertex properties in sequence and execute the instruction upon the streamed vertex properties.

### Claim 3 (depends on 1)

The processor of claim 1, wherein the graph accelerator further includes a parallel execution pipeline, the parallel execution pipeline including circuitry to partition vertex execution into a plurality of parallel execution pipelines.

### Claim 4 (depends on 1)

The processor of claim 1, wherein the graph accelerator further includes:
an on-chip memory including granular data formats corresponding to vertex and edge data; and
circuitry to store intermediate vertex and edge values on the on-chip memory.

### Claim 5 (depends on 1)

The processor of claim 1, wherein the graph accelerator further includes an edge table implanted in hardware, the edge table to represent a candidate graph in compressed form.

### Claim 6 (depends on 1)

The processor of claim 1, wherein the graph accelerator further includes:
an edge table implanted in hardware, the edge table to represent a candidate graph in compressed form; and
circuitry to access the edge table to fetch edge information to execute the instruction.

### Claim 7 (depends on 1)

The processor of claim 1, wherein:
the graph accelerator further includes an edge table implanted in hardware, the edge table to represent a candidate graph in compressed form; and
an entry in the edge table is to associate a vertex identifier and a starting edge pointer address.

### Claim 8

An accelerator circuit, comprising circuitry to:
execute an instruction, the instruction to perform a graph analytic function; and
process graph vertices and graph edges as datatypes; and
pass results of the instruction to a memory of a system.

### Claim 9 (depends on 8)

The accelerator circuit of claim 8, further comprising circuitry to stream inputs of vertex properties in sequence and execute the instruction upon the streamed vertex properties.

### Claim 10 (depends on 8)

The accelerator circuit of claim 8, further comprising a parallel execution pipeline, the parallel execution pipeline including circuitry to partition vertex execution into a plurality of parallel execution pipelines.

### Claim 11 (depends on 8)

The accelerator circuit of claim 8, further comprising:
an on-chip memory including granular data formats corresponding to vertex and edge data; and
circuitry to store intermediate vertex and edge values on the on-chip memory.

### Claim 12 (depends on 8)

The accelerator circuit of claim 8, further comprising an edge table implanted in hardware, the edge table to represent a candidate graph in compressed form.

### Claim 13 (depends on 8)

The accelerator circuit of claim 8, further comprising:
an edge table implanted in hardware, the edge table to represent a candidate graph in compressed form; and
circuitry to access the edge table to fetch edge information to execute the instruction.

### Claim 14 (depends on 8)

The accelerator circuit of claim 8, wherein:
the accelerator circuit further comprises an edge table implanted in hardware, the edge table to represent a candidate graph in compressed form; and
an entry in the edge table is to associate a vertex identifier and a starting edge pointer address.

### Claim 15

A method, comprising:
offloading execution of an instruction to a graph accelerator, the instruction to perform a graph analytic function;
in the graph accelerator, processing graph vertices and graph edges as datatypes; and
pass results of the instruction to a memory of a system.

### Claim 16 (depends on 15)

The method of claim 15, further comprising, in the graph accelerator, streaming inputs of vertex properties in sequence and execute the instruction upon the streamed vertex properties.

### Claim 17 (depends on 15)

The method of claim 15, further comprising, in the graph accelerator, executing the instruction through a parallel execution pipeline, the parallel execution pipeline including circuitry to partition vertex execution into a plurality of parallel execution pipelines.

### Claim 18 (depends on 15)

The method of claim 15, further comprising storing intermediate vertex and edge values on an on-chip memory in the graph accelerator, the on-chip memory including granular data formats corresponding to vertex and edge data.

### Claim 19 (depends on 15)

The method of claim 15, further comprising accessing an edge table to fetch edge information to execute the instruction, the edge table implanted in hardware, the edge table to represent a candidate graph in compressed form.

### Claim 20 (depends on 15)

The method of claim 15, further comprising accessing an edge table implanted in hardware, the edge table to represent a candidate graph in compressed form, wherein accessing the edge table includes obtaining a starting edge pointer from an entry associating the starting edge pointer with a vertex identifier.