# US 2017/0286121 A1 · Apparatus and method for re-execution of faulting operations

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- Number: US 2017/0286121 A1
- Document ID: US20170286121A1
- Status: Published application
- Kind: A1
- Application number: 15/089,095
- Filed: 2016-04-01
- Published: 2017-10-05
- Earliest claimed: 2016-04-01
- Inventors: Gur HILDESHEIM; Igor YANOVER; Stanislav SHWARTSMAN; Raanan SADE; Ron RAIS
- Web page: https://patentgrep.com/patent/US20170286121A1

## CPC

- G06F 9/38585: {with result invalidation, e.g. nullification}
- G06F 9/3861: {Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00)}
- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/30101: {Special purpose registers}
- G06F 9/3016: {Decoding the operand specifier, e.g. specifier format}
- G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An apparatus and method are described for at-retirement re-execution of faulting operations. For example, one embodiment of a processor comprises: an out-of-order engine to schedule and dispatch operations to an execution unit at least some of the operations comprising load operations to load data from a system memory and store operations to store data to the system memory; a first circuit to determine whether a current load/store operation is at retirement; a second circuit to cause logging circuitry and/or fault registers to be active when a load/store operation has been dispatched at retirement, wherein upon detection of a fault condition associated with the load/store operation, data associated with the fault is to be written to the logging circuitry and/or fault registers, the second circuit to cause the logging circuitry and/or fault registers to be inactive if the load/store operation has not be dispatched at retirement.

## Claims

### Claim 1

A processor comprising:
an out-of-order engine to schedule and dispatch operations to an execution unit at least some of the operations comprising load operations to load data from a system memory and store operations to store data to the system memory;
a first circuit to determine whether a current load/store operation is at retirement;
a second circuit to cause logging circuitry and/or fault registers to be active when a load/store operation has been dispatched at retirement, wherein upon detection of a fault condition associated with the load/store operation, data associated with the fault is to be written to the logging circuitry and/or fault registers, the second circuit to cause the logging circuitry and/or fault registers to be inactive if the load/store operation has not been dispatched at retirement.

### Claim 2 (depends on 1)

The processor as in claim 1 wherein data associated with the fault condition is not written to the logging circuitry and/or fault registers when the load/store operation has not been dispatched at retirement.

### Claim 3 (depends on 2)

The processor as in claim 2 wherein a operation at retirement comprises the oldest non-retired operation in a particular thread being processed by the out-of-order engine.

### Claim 4 (depends on 3)

The processor as in claim 3 further comprising:
a data translation lookaside buffer (DTLB) associated with the logging circuitry and/or fault registers.

### Claim 5 (depends on 4)

The processor as in claim 4 wherein if the load/store operation is not at retirement, then the load/store operation to be redispatched by the out-of-order engine only when the load/store operation is the next operation to retire.

### Claim 6 (depends on 1)

The processor as in claim 1 wherein the load/store operations comprise load store micro-operations (uops).

### Claim 7 (depends on 6)

The processor as in claim 6 further comprising:
a fetch circuit to fetch a load/store macroinstruction; and
a decoder circuit to decode the load/store macroinstruction and responsively generate the load/store uop.

### Claim 8 (depends on 7)

The processor as in claim 7 wherein the first circuit and the second circuit are integrated within a memory subsystem of the processor.

### Claim 9

A method comprising:
scheduling and dispatching operations to an execution unit at least some of the operations comprising load operations to load data from a system memory and store operations to store data to the system memory;
determining whether a current load/store operation has faulted and, if not, then continuing execution of the load/store operation;
determining whether the current load/store operation is at retirement if the current load/store operation has faulted;
if the current load/store operation which has faulted is not at retirement, then scheduling the uop to be re-dispatched only when it is the next uop to retire;
causing logging circuitry and/or fault registers to be active when a load/store operation has been dispatched at retirement and causing the logging circuitry and/or fault registers to be inactive if the load/store operation has not been dispatched at retirement.

### Claim 10 (depends on 9)

The method as in claim 9 wherein upon detection of a fault condition associated with the current load/store operation, data associated with the fault is to be written to the logging circuitry and/or fault registers.

### Claim 11 (depends on 10)

The method as in claim 10 wherein data associated with the fault condition is not written to the logging circuitry and/or fault registers when the load/store operation has not been dispatched at retirement.

### Claim 12 (depends on 11)

The method as in claim 11 wherein an operation at retirement comprises the oldest non-retired operation in a particular thread being processed by the out-of-order engine.

### Claim 13 (depends on 12)

The method as in claim 12 further comprising:
a data translation lookaside buffer (DTLB) associated with the logging circuitry and/or fault registers.

### Claim 14 (depends on 13)

The method as in claim 13 wherein if the load/store operation is not at retirement, then the load/store operation is to be re-dispatched only when the load/store operation is the next operation to retire.

### Claim 15 (depends on 14)

The method as in claim 14 wherein the load/store operations comprise load store micro-operations (uops).

### Claim 16 (depends on 15)

The method as in claim 15 further comprising:
fetching a load/store macroinstruction; and
decoding the load/store macroinstruction and responsively generating the load/store uop.

### Claim 17

A system comprising:
a memory to store instructions and data;
a processor to execute the instructions and process the data;
a graphics processor to perform graphics operations in response to graphics instructions;
a network interface to receive and transmit data over a network;
an interface for receiving user input from a mouse or cursor control device, the plurality of cores executing the instructions and processing the data responsive to the user input;
the processor comprising:
an out-of-order engine to schedule and dispatch operations to an execution unit at least some of the operations comprising load operations to load data from a system memory and store operations to store data to the system memory;
a first circuit to determine whether a current load/store operation is at retirement;
a second circuit to cause logging circuitry and/or fault registers to be active when a load/store operation has been dispatched at retirement, wherein upon detection of a fault condition associated with the load/store operation, data associated with the fault is to be written to the logging circuitry and/or fault registers, the second circuit to cause the logging circuitry and/or fault registers to be inactive if the load/store operation has not been dispatched at retirement.

### Claim 18 (depends on 17)

The system as in claim 17 wherein data associated with the fault condition is not written to the logging circuitry and/or fault registers when the load/store operation has not been dispatched at retirement.

### Claim 19 (depends on 18)

The system as in claim 18 wherein a operation at retirement comprises the oldest non-retired operation in a particular thread being processed by the out-of-order engine.

### Claim 20 (depends on 19)

The system as in claim 19 further comprising:
a data translation lookaside buffer (DTLB) associated with the logging circuitry and/or fault registers.

### Claim 21 (depends on 20)

The system as in claim 20 wherein if the load/store operation is not at retirement, then the load/store operation to be redispatched by the out-of-order engine only when the load/store operation is the next operation to retire.

### Claim 22 (depends on 17)

The system as in claim 17 wherein the load/store operations comprise load store micro-operations (uops).

### Claim 23 (depends on 22)

The system as in claim 22 further comprising:
a fetch circuit to fetch a load/store macroinstruction; and
a decoder circuit to decode the load/store macroinstruction and responsively generate the load/store uop.

### Claim 24 (depends on 23)

The system as in claim 23 wherein the first circuit and the second circuit are integrated within a memory subsystem of the system.