# US 2017/0286115 A1 · Apparatus and method for non-serializing split locks > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0286115 A1 - Document ID: US20170286115A1 - Status: Published application - Kind: A1 - Application number: 15/089,264 - Filed: 2016-04-01 - Published: 2017-10-05 - Earliest claimed: 2016-04-01 - Assignees: Intel Corporation - Inventors: JAMES A. COLEMAN; GARRETT DROWN - Web page: https://patentgrep.com/patent/US20170286115A1 ## CPC - G06F 9/30047: {Prefetch instructions; cache control instructions} - G06F 9/3005: {to perform operations for flow control} - G06F 9/323: {for indirect branch instructions} - G06F 9/3834: {Maintaining memory consistency} - G06F 9/52: Program synchronisation; Mutual exclusion, e.g. by means of semaphores - G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means - G06F 12/084: with a shared cache - G06F 12/0875: with dedicated cache, e.g. instruction or stack - G06F 2212/452: Instruction code - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus and method are described for performing split lock operations in a multi-core processor. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions, each core comprising a core cache to cache data during instruction execution; a shared cache to be shared by two or more of the plurality of cores; a locking agent on a first core to initiate a split lock operation in response to detecting a transaction targeting at least two cache lines, the locking agent to transmit a request for the two cache lines to be set to an Exclusive state; at least one coherence enforcement engine to receive the request from the locking agent and to responsively cause any copies of the two cache lines in other cores to be invalidated; the locking agent to permit the transaction targeting the two cache lines to complete upon receipt of an indication that the cache lines are in the Exclusive state and, upon completion of the transaction, to transmit an indication that the transaction is complete to the coherence enforcement engine. ## Claims ### Claim 1 A processor comprising: a plurality of cores to execute instructions, each core comprising a core cache to cache data during instruction execution; a shared cache to be shared by two or more of the plurality of cores; a locking agent on a first core to initiate a split lock operation in response to detecting a transaction targeting at least two cache lines, the locking agent to transmit a request for the two cache lines to be set to an Exclusive state; at least one coherence enforcement engine to receive the request from the locking agent and to responsively cause any copies of the two cache lines in other cores to be invalidated; the locking agent to permit the transaction targeting the two cache lines to complete upon receipt of an indication that the cache lines are in the Exclusive state and, upon completion of the transaction, to transmit an indication that the transaction is complete to the coherence enforcement engine. ### Claim 2 (depends on 1) The processor as in claim 1 wherein to initiate the split lock operation, the locking agent is to transmit a request for the split lock operation to a lock master, the lock master to transmit a response to the locking agent to grant the split lock operation. ### Claim 3 (depends on 2) The processor as in claim 2 wherein the locking agent is to transmit an indication to release the split lock to the lock master upon completion of the transaction involving the two cache lines. ### Claim 4 (depends on 1) The processor as in claim 1 wherein the coherence enforcement engine is to enqueue any new requests directed to the two cache lines prior to the completion of the transaction involving the two cache lines, the coherence enforcement engine to process the new requests after receiving the indication that the transaction is complete from the locking agent. ### Claim 5 (depends on 4) The processor as in claim 4 wherein to responsively cause any copies of the two cache lines in other cores to be invalidated, the coherence enforcement engine is to transmit cache line invalidate commands to caching agents of the other cores. ### Claim 6 (depends on 5) The processor as in claim 5 wherein the invalidate commands comprise write-back invalidate (WBINV) commands to cause all caching agents of caches containing the two cache lines to invalidate the cache lines and write back any modifications to the cache lines to memory. ### Claim 7 (depends on 1) The processor as in claim 1 wherein the core cache comprises a Level 1 (L1) cache and wherein the shared cache comprises a Level 3 (L3) cache. ### Claim 8 A method comprising: initiating a split lock operation in a first core in response to detecting a transaction targeting at least two cache lines of a cache of the first core; transmitting a request for the two cache lines to be set to an Exclusive state; responsively causing any copies of the two cache lines in other cores to be invalidated; permitting the transaction targeting the two cache lines to complete upon receipt of an indication that the cache lines are in the Exclusive state; and upon completion of the transaction, transmitting an indication that the transaction is complete. ### Claim 9 (depends on 8) The method as in claim 8 wherein to initiate the split lock operation, a locking agent of the first core is to transmit a request for the split lock operation to a lock master, the lock master to transmit a response to the locking agent to grant the split lock operation. ### Claim 10 (depends on 9) The method as in claim 9 wherein the locking agent is to transmit an indication to release the split lock to the lock master upon completion of the transaction involving the two cache lines. ### Claim 11 (depends on 8) The method as in claim 8 further comprising: enqueuing any new requests directed to the two cache lines prior to the completion of the transaction involving the two cache lines; and processing the new requests after receiving the indication that the transaction is complete from the locking agent. ### Claim 12 (depends on 11) The method as in claim 11 wherein to responsively cause any copies of the two cache lines in other cores to be invalidated, cache line invalidate commands are transmitted to caching agents of the other cores. ### Claim 13 (depends on 12) The method as in claim 12 wherein the invalidate commands comprise write-back invalidate (WBINV) commands to cause all caching agents of caches containing the two cache lines to invalidate the cache lines and write back any modifications to the cache lines to memory. ### Claim 14 (depends on 8) The method as in claim 8 wherein the cache of the first core comprises a Level 1 (L1) cache. ### Claim 15 A system comprising: a memory to store instructions and data; a processor to execute the instructions and process the data; a graphics processor to perform graphics operations in response to graphics instructions; a network interface to receive and transmit data over a network; an interface for receiving user input from a mouse or cursor control device, the plurality of cores executing the instructions and processing the data responsive to the user input; the processor comprising: a plurality of cores to execute instructions, each core comprising a core cache to cache data during instruction execution; a shared cache to be shared by two or more of the plurality of cores; a locking agent on a first core to initiate a split lock operation in response to detecting a transaction targeting at least two cache lines, the locking agent to transmit a request for the two cache lines to be set to an Exclusive state; at least one coherence enforcement engine to receive the request from the locking agent and to responsively cause any copies of the two cache lines in other cores to be invalidated; the locking agent to permit the transaction targeting the two cache lines to complete upon receipt of an indication that the cache lines are in the Exclusive state and, upon completion of the transaction, to transmit an indication that the transaction is complete to the coherence enforcement engine. ### Claim 16 (depends on 15) The system as in claim 15 wherein to initiate the split lock operation, the locking agent is to transmit a request for the split lock operation to a lock master, the lock master to transmit a response to the locking agent to grant the split lock operation. ### Claim 17 (depends on 16) The system as in claim 16 wherein the locking agent is to transmit an indication to release the split lock to the lock master upon completion of the transaction involving the two cache lines. ### Claim 18 (depends on 15) The system as in claim 15 wherein the coherence enforcement engine is to enqueue any new requests directed to the two cache lines prior to the completion of the transaction involving the two cache lines, the coherence enforcement engine to process the new requests after receiving the indication that the transaction is complete from the locking agent. ### Claim 19 (depends on 18) The system as in claim 18 wherein to responsively cause any copies of the two cache lines in other cores to be invalidated, the coherence enforcement engine is to transmit cache line invalidate commands to caching agents of the other cores. ### Claim 20 (depends on 19) The system as in claim 19 wherein the invalidate commands comprise write-back invalidate (WBINV) commands to cause all caching agents of caches containing the two cache lines to invalidate the cache lines and write back any modifications to the cache lines to memory. ### Claim 21 (depends on 15) The system as in claim 15 wherein the core cache comprises a Level 1 (L1) cache and wherein the shared cache comprises a Level 3 (L3) cache.