# US 2017/0286114 A1 · Processors, methods, and systems to allocate load and store buffers based on instruction type > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0286114 A1 - Document ID: US20170286114A1 - Status: Published application - Kind: A1 - Application number: 15/089,533 - Filed: 2016-04-02 - Published: 2017-10-05 - Earliest claimed: 2016-04-02 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Andrew J. Herdrich; Yipeng Wang; Ren Wang; Tsung-Yuan Charles Tai; Jr-Shian Tsai - Web page: https://patentgrep.com/patent/US20170286114A1 ## CPC - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/30047: {Prefetch instructions; cache control instructions} - G06F 9/3824: {Operand accessing} - G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution} - G06F 12/0804: with main memory updating (G06F12/0806 takes precedence) - G06F 12/0862: with prefetch - G06F 2212/6028: Prefetching based on hints or prefetch instructions - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A processor of an aspect includes a decode unit to decode memory access instructions of a first type and to output corresponding memory access operations, and to decode memory access instructions of a second type and to output corresponding memory access operations. The processor also includes a load store queue coupled with the decode unit. The load store queue includes a load buffer that is to have a plurality of load buffer entries, and a store buffer that is to have a plurality of store buffer entries. The load store queue also includes a buffer entry allocation controller coupled with the load buffer and coupled with the store buffer. The buffer entry allocation controller is to allocate load and store buffer entries based at least in part on whether memory access operations correspond to memory access instructions of the first type or of the second type. Other processors, methods, and systems, are also disclosed. ## Claims ### Claim 1 A processor comprising: a decode unit to decode memory access instructions of a first type and to output corresponding memory access operations, and to decode memory access instructions of a second type and to output corresponding memory access operations; and a load store queue coupled with the decode unit, the load store queue including: a load buffer that is to have a plurality of load buffer entries; a store buffer that is to have a plurality of store buffer entries; and a buffer entry allocation controller coupled with the load buffer and coupled with the store buffer, the buffer entry allocation controller to allocate load and store buffer entries based at least in part on whether memory access operations correspond to memory access instructions of the first type or of the second type. ### Claim 2 (depends on 1) The processor of claim 1, wherein the buffer entry allocation controller, for a given memory access operation that is to correspond to a memory access instruction of the second type, is not to allocate a load buffer entry, and is not to allocate a store buffer entry. ### Claim 3 (depends on 1) The processor of claim 1, wherein the buffer entry allocation controller, for a given memory access operation that corresponds to a given memory access instruction of the second type, is to determine whether to allocate at least one of a load buffer entry and a store buffer entry. ### Claim 4 (depends on 3) The processor of claim 3, wherein the buffer entry allocation controller is to: determine to allocate an entry in a respective one of the load and store buffers when current allocated entries for said respective one of the load and store buffers is below a threshold; and otherwise determine not to allocate the entry in said respective one of the load and store buffers. ### Claim 5 (depends on 3) The processor of claim 3, wherein the load store queue, when the given memory access operation comprises a given load operation, is to output the given load operation without said at least one of the load and store buffer entries being allocated by the buffer entry allocation controller, when: (1) there is no dependency between the given load operation and operations that correspond to already allocated entries in the load and store buffers; and (2) resources are available to output the given load operation. ### Claim 6 (depends on 1) The processor of claim 1, wherein the buffer entry allocation controller, for each memory access operation that corresponds to a memory access instruction of the first type, is to unconditionally allocate at least one of a load buffer entry and a store buffer entry. ### Claim 7 (depends on 1) The processor of claim 1, wherein the load store queue further comprises a bypass buffer coupled with the buffer entry allocation controller, the bypass buffer to have a plurality of bypass buffer entries. ### Claim 8 (depends on 7) The processor of claim 7, wherein the buffer entry allocation controller is to allocate bypass buffer entries for memory access operations that correspond to memory access instructions of the second type, but is not to allocate bypass buffer entries for memory access operations that correspond to memory access instructions of the first type. ### Claim 9 (depends on 7) The processor of claim 7, wherein the bypass buffer is to be more weakly memory ordered than the load and store buffers. ### Claim 10 (depends on 7) The processor of claim 7, wherein the bypass buffer is to have more relaxed memory dependency checking than the load and store buffers. ### Claim 11 (depends on 7) The processor of claim 7, wherein the buffer entry allocation controller, for a given load operation that corresponds to a given memory access instruction of the second type, is to allocate a bypass buffer entry for the given load operation when at least one of: (1) there is a dependency between the given load operation and at least one operation corresponding to an already allocated entry in one of the load and store buffers; and (2) resources are not currently available to output the given load operation ### Claim 12 (depends on 7) The processor of claim 7, wherein the buffer entry allocation controller, for a given store operation that corresponds to a given memory access instruction of the second type, is to allocate a bypass buffer entry for the given store operation. ### Claim 13 (depends on 1) The processor of claim 1, wherein the memory access instructions of the first type are to include at least one load instruction and at least one store instruction, and wherein the memory access instructions of the second type are to include at least one of a prefetch instruction, a cache line flush instruction, a cache line write back instruction, an instruction to move a cache line between caches, and a persistent commit instruction. ### Claim 14 A method performed by a processor, the method comprising: receiving memory access instructions of a first type; receiving memory access instructions of a second type; and allocating load buffer entries of a load buffer and store buffer entries of a store buffer for memory access operations based at least in part on whether the memory access operations correspond to the memory access instructions of the first type or the second type. ### Claim 15 (depends on 14) The method of claim 14, wherein said allocating, for a given memory access operation corresponding to a memory access instruction of the second type, comprises not allocating a load buffer entry, and not allocating a store buffer entry. ### Claim 16 (depends on 14) The method of claim 14, wherein said allocating, for a given memory access operation corresponding to a given memory access instruction of the second type, comprises determining whether to allocate at least one of a load buffer entry and a store buffer entry. ### Claim 17 (depends on 16) The method of claim 16, wherein said allocating comprises: determining to allocate an entry in a respective one of the load and store buffers when current allocated entries for said respective one of the load and store buffers is below a threshold; and otherwise determining not to allocate the entry in said respective one of the load and store buffers. ### Claim 18 (depends on 16) The method of claim 16, further comprising, when the given memory access operation comprises a given load operation, outputting the given load operation without allocating said at least one of the load and store buffer entries, when: (1) there is no dependency between the given load operation and operations corresponding to already allocated entries in the load and store buffers; and (2) resources are available to output the given load operation. ### Claim 19 (depends on 14) The method of claim 14, further comprising allocating bypass buffer entries in a bypass buffer for memory access operations corresponding to memory access instructions of the second type, but not allocating bypass buffer entries for memory access operations corresponding to memory access instructions of the first type. ### Claim 20 (depends on 19) The method of claim 19, further comprising enforcing a memory ordering model for the bypass buffer that is weaker than a memory order model enforced for the load and store buffers. ### Claim 21 (depends on 14) The method of claim 14, wherein said receiving the memory access instructions of the first type comprises receiving at least one load instruction and at least one store instruction, and wherein receiving the memory access instructions of the second type comprises receiving at least one of a prefetch instruction, a cache line flush instruction, a cache line write back instruction, an instruction to move a cache line between caches, and a persistent commit instruction. ### Claim 22 A computer system comprising: an interconnect; a processor coupled with the interconnect, the processor to receive memory access instructions of a first type and memory access instructions of a second type, the processor comprising: a load store queue including: a load buffer that is to have a plurality of load buffer entries; a store buffer that is to have a plurality of store buffer entries; and wherein the load store queue is to allocate load and store buffer entries for memory access operations based at least in part on whether the memory access operations correspond to the memory access instructions of the first type or the second type; and a dynamic random access memory (DRAM) coupled with the interconnect. ### Claim 23 (depends on 22) The computer system of claim 22, wherein the load store queue, for a given memory access operation that is to correspond to a memory access instruction of the second type, is not to allocate a load buffer entry, and is not to allocate a store buffer entry. ### Claim 24 (depends on 22) The computer system of claim 22, wherein the load store queue, for a given memory access operation that corresponds to a given memory access instruction of the second type, is to determine whether to allocate at least one of a load buffer entry and a store buffer entry. ### Claim 25 (depends on 22) The computer system of claim 22, wherein the load store queue further comprises a bypass buffer coupled with the buffer entry allocation controller, the bypass buffer to have a plurality of bypass buffer entries, and wherein the load store queue is to allocate bypass buffer entries to memory access operations that correspond to the memory access instructions of the second type but is not to allocate bypass buffer entries to memory access operations that correspond to the memory access instructions of the first type.