# US 2017/0286113 A1 · Processors, methods, systems, and instructions to atomically store to memory data wider than a natively supported data width > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0286113 A1 - Document ID: US20170286113A1 - Status: Published application - Kind: A1 - Application number: 15/089,525 - Filed: 2016-04-02 - Published: 2017-10-05 - Earliest claimed: 2016-04-02 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Vedvyas Shanbhogue; Stephen J. Robinson; Christopher D. Bryant; Jason W. Brandt - Web page: https://patentgrep.com/patent/US20170286113A1 ## CPC - G06F 15/8007: {single instruction multiple data [SIMD] multiprocessors} - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/3004: {to perform operations on memory} - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/30112: {comprising data of variable length} - G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]} - G06F 9/3888: {controlled by a single instruction for multiple threads [SIMT] in parallel} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location. ## Claims ### Claim 1 A processor comprising: a widest set of data registers corresponding to a given logical processor, each of the data registers of the widest set having a first width in bits; a decode unit corresponding to the given logical processor to decode instructions that specify the data registers of the widest set, and to decode an atomic store to memory instruction, the atomic store to memory instruction to indicate data that is to have a second width in bits that is wider than the first width in bits of each of the data registers of the widest set, and the atomic store to memory instruction to indicate memory address information associated with a memory location; and an execution unit coupled with the decode unit, the execution unit, in response to the atomic store to memory instruction, to atomically store the indicated data to the memory location. ### Claim 2 (depends on 1) The processor of claim 1, wherein the execution unit comprises a staging buffer, and wherein the execution unit, in response to the atomic store to memory instruction, is to: sequentially store a plurality of portions that are to collectively represent a total amount of the indicated data to the staging buffer; and concurrently store the total amount of the indicated data from the staging buffer after the total amount of the indicated data has been stored in the staging buffer. ### Claim 3 (depends on 2) The processor of claim 2, further comprising a write combining buffer, and wherein the execution unit, in response to the atomic store to memory instruction, is to concurrently store the total amount of the indicated data from the staging buffer to the write combining buffer. ### Claim 4 (depends on 3) The processor of claim 3, wherein the execution unit, in response to the atomic store to memory instruction, is to configure the write combining buffer for eviction after the plurality of portions of the indicated data have been stored to the write combining buffer. ### Claim 5 (depends on 3) The processor of claim 3, wherein the execution unit, in response to the atomic store to memory instruction, is to configure the write combining buffer to not allow a younger store operation to merge with the write combining buffer after the plurality of portions of the indicated data have been stored to the write combining buffer. ### Claim 6 (depends on 1) The processor of claim 1, wherein the execution unit, in response to the atomic store to memory instruction, is to signal one of a breakpoint configured on, a segment limit violation for, a canonical address form violation for, and a range based violation for, any bytes from a first byte to a last byte of the memory location where the data is to be atomically stored, when the atomic store to memory instruction retires. ### Claim 7 (depends on 1) The processor of claim 1, wherein the execution unit, in response to the atomic store to memory instruction, is to make the atomic store of the data non-forwardable and is to force a memory type associated with the atomically stored data to be uncacheable speculative write combining (USWC) irrespective of an underlying memory type. ### Claim 8 (depends on 1) The processor of claim 1, wherein the first and second widths are one of: the first width is 128-bits and the second width is 256-bits; the first width is 128-bits and the second width is 512-bits; the first width is 128-bits and the second width is 1024-bits; the first width is 256-bits and the second width is 512-bits; and the first width is 256-bits and the second width is 1024-bits. ### Claim 9 (depends on 1) The processor of claim 1, wherein the decode unit is to decode the atomic store to memory instruction that is to indicate second memory address information associated with a second different memory location from where the indicated data is to be loaded in response to the atomic store to memory instruction. ### Claim 10 (depends on 1) The processor of claim 1, wherein the decode unit is to decode the atomic store to memory instruction that is to indicate a plurality of the data registers of the widest set that are initially to be used to store the indicated data. ### Claim 11 (depends on 1) The processor of claim 1, further comprising a retire unit, and wherein the retire unit is to wait to retire the atomic store to memory instruction until receipt of a response, wherein the response is to indicate that the atomic store has been fully observed and is now fully coherent. ### Claim 12 (depends on 1) The processor of claim 1, wherein the second width is wider than a width in bits of a widest operation, which is one of an arithmetic operation, a logical operation, and an arithmetic and logical operation, that the given logical processor is able to perform on one or more packed data operands. ### Claim 13 (depends on 1) The processor of claim 1, wherein the second width is wider than a width in bits of a widest packed data operand that to be indicated by any one of any packed data add instructions that the decode unit is to decode and any packed data multiply instructions that the decode unit is to decode. ### Claim 14 A method performed by a processor comprising: receiving an atomic store to memory instruction at a given logical processor of the processor, the atomic store to memory instruction indicating data that is wider in bits than a widest data register that instructions of an instruction set of the given logical processor are able to specify, and the atomic store to memory instruction indicating memory address information associated with a memory location; and atomically storing the indicated data to the memory location, in response to the atomic store to memory instruction. ### Claim 15 (depends on 14) The method of claim 14, wherein said atomically storing comprises atomically storing the indicated data having a width of at least 512-bits to the memory location, and wherein a width of the widest data register is no more than 256-bits. ### Claim 16 (depends on 14) The method of claim 14, wherein said atomically storing further comprises, in response to the atomic store to memory instruction: sequentially storing a plurality of portions collectively representing a total amount of the indicated data to a staging buffer; and concurrently storing the total amount of the indicated data from the staging buffer after the total amount of the indicated data has been stored in the staging buffer. ### Claim 17 (depends on 16) The method of claim 16, wherein said concurrently storing comprises concurrently storing the total amount of the indicated data from the staging buffer to a write combining buffer, and wherein said atomically storing further comprises, in response to the atomic store to memory instruction: configuring the write combining buffer to not allow a younger store operation to merge with the write combining buffer after the plurality of portions of the indicated data have been stored to the write combining buffer; and configuring the write combining buffer for eviction after the plurality of portions of the indicated data have been stored to the write combining buffer. ### Claim 18 (depends on 14) The method of claim 14, wherein said atomically storing the indicated data to the memory location is used to assign work to an accelerator device. ### Claim 19 (depends on 14) The method of claim 14, further comprising detecting and signaling one of a breakpoint, a segment limit violation, and a range based violation, on any bytes of the memory location when the data is atomically stored, when the atomic store to memory instruction commits. ### Claim 20 (depends on 14) The method of claim 14, wherein said receiving comprises receiving the atomic store to memory instruction that indicates memory address information associated with a second memory location from where the indicated data is loaded in response to the atomic store to memory instruction. ### Claim 21 A computer system comprising: an interconnect; a processor coupled with the interconnect, the processor having a given core having a widest set of data registers, each of the data registers of the widest set having a first width in bits, the given core to receive an atomic store to memory instruction that is to indicate data that is to have a second width in bits that is wider than the first width of each of the data registers of the widest set, and the atomic store to memory instruction to indicate memory address information associated with a memory location, the processor, in response to the atomic store to memory instruction, to atomically store the indicated data to the memory location; and a dynamic random access memory (DRAM) coupled with the interconnect, the DRAM storing a set of instructions to use different instances of the atomic store to memory instruction to submit work to another device. ### Claim 22 (depends on 21) The computer system of claim 21, wherein the processor comprises a staging buffer, and a write combining buffer, and wherein the processor, in response to the atomic store to memory instruction, is to: sequentially store a plurality of portions that are to collectively represent a total amount of the indicated data to the staging buffer; and concurrently store the total amount of the indicated data from the staging buffer to one of another storage location and an interconnect after the total amount of the indicated data has been stored in the staging buffer. ### Claim 23 (depends on 21) The computer system of claim 21, wherein the first width is no more than 256-bits, and the second width is at least 512-bits. ### Claim 24 A processor comprising: a decode unit corresponding to a given logical processor, the decode unit to decode an atomic store to memory instruction, the atomic store to memory instruction to indicate data, and the atomic store to memory instruction to indicate memory address information associated with a memory location; and an execution unit coupled with the decode unit, the execution unit, in response to the atomic store to memory instruction, to atomically store the indicated data to the memory location, wherein a width in bits of the data that is to be atomically stored in response to the atomic store to memory instruction is to be wider than a width in bits of data to be atomically loaded by any instruction the decoder is able to decode. ### Claim 25 (depends on 24) The processor of claim 24, wherein the execution unit comprises a staging buffer, and wherein the execution unit, in response to the atomic store to memory instruction, is to: sequentially store a plurality of portions that are to collectively represent a total amount of the indicated data to the staging buffer; and concurrently store the total amount of the indicated data from the staging buffer after the total amount of the indicated data has been stored in the staging buffer.