# US 2017/0286111 A1 · Instruction, Circuits, and Logic for Data Capture for Software Monitoring and Debugging

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- Number: US 2017/0286111 A1
- Document ID: US20170286111A1
- Status: Published application
- Kind: A1
- Application number: 15/089,179
- Filed: 2016-04-01
- Published: 2017-10-05
- Earliest claimed: 2016-04-01
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Cristiano L. Pereira; Gilles A. Pokam; Shiliang Hu; Beeman C. Strong
- Web page: https://patentgrep.com/patent/US20170286111A1

## CPC

- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 11/3034: {where the computing system component is a storage system, e.g. DASD based or network based (digital input from or digital output to record carriers G06F3/06; digital recording or reproducing G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097)}
- G06F 11/3466: {Performance evaluation by tracing or monitoring}
- G06F 12/0842: for multiprocessing or multitasking
- G06F 12/0888: using selective caching, e.g. bypass
- G06F 2201/865: Monitoring of software
- G06F 2212/452: Instruction code
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A processor includes a front end including circuitry to receive an instruction to monitor execution of a thread, a decoder including circuitry to decode the instruction, a scheduler including circuitry to schedule the instruction, a retirement unit including circuitry to retire the instruction, and a core. The core includes circuitry to, based on execution of the instruction, monitor execution of the thread, identify an attempted read of an address during execution of the thread, determine whether a value at the address was previously read during monitoring of the execution of the thread, log the attempted read based on a determination that the value at the address was not previously read during monitoring of the execution of the thread, and omit logging of the attempted read based on a determination that the value at the address was previously read during monitoring of the execution of the thread.

## Claims

### Claim 1

A processor, comprising:
a front end including circuitry to receive an instruction to monitor execution of a thread;
a decoder including circuitry to decode the instruction;
a scheduler including circuitry to schedule the instruction;
a retirement unit including circuitry to retire the instruction; and
a core including circuitry to, based on execution of the instruction:
monitor execution of the thread;
identify an attempted read of an address during execution of the thread;
determine whether a value at the address was previously read during monitoring of the execution of the thread;
log the attempted read based on a determination that the value at the address was not previously read during monitoring of the execution of the thread; and
omit logging of the attempted read based on a determination that the value at the address was previously read during monitoring of the execution of the thread.

### Claim 2 (depends on 1)

The processor of claim 1, wherein the core further includes circuitry to determine whether the value at the address was previously read by tracking metadata in a cache associated with the address.

### Claim 3 (depends on 1)

The processor of claim 1, wherein the core further includes circuitry to determine whether the value at the address was previously read by tracking metadata in a fill buffer associated with the address.

### Claim 4 (depends on 1)

The processor of claim 1, wherein the core further includes circuitry to log additional attempted accesses of memory necessary to reconstruct a trace of execution.

### Claim 5 (depends on 1)

The processor of claim 1, wherein the core further includes circuitry to clear an indication that the value at the address was previously read upon a cache line eviction.

### Claim 6 (depends on 1)

The processor of claim 1, wherein the core further includes circuitry to clear an indication that the value at the address was previously read upon a cache line invalidation.

### Claim 7 (depends on 1)

The processor of claim 1, wherein the core further includes circuitry to:
receive a previous attempt to read the value at the address;
set an indication that the value at the address was previously read based on the previous attempt; and
use the indication to determine whether the value at the address was previously read for execution of the attempted read.

### Claim 8

A system, comprising:
a processor;
a front end including circuitry to receive an instruction to monitor execution of a thread;
a decoder including circuitry to decode the instruction;
a scheduler including circuitry to schedule the instruction;
a retirement unit including circuitry to retire the instruction; and
a core including circuitry to, based on execution of the instruction:
monitor execution of the thread;
identify an attempted read of an address during execution of the thread;
determine whether a value at the address was previously read during monitoring of the execution of the thread;
log the attempted read based on a determination that the value at the address was not previously read during monitoring of the execution of the thread; and
omit logging of the attempted read based on a determination that the value at the address was previously read during monitoring of the execution of the thread.

### Claim 9 (depends on 8)

The system of claim 8, wherein the core further includes circuitry to determine whether the value at the address was previously read by tracking metadata in a cache associated with the address.

### Claim 10 (depends on 8)

The system of claim 8, wherein the core further includes circuitry to determine whether the value at the address was previously read by tracking metadata in a fill buffer associated with the address.

### Claim 11 (depends on 8)

The system of claim 8, wherein the core further includes circuitry to log additional attempted accesses of memory necessary to reconstruct a trace of execution.

### Claim 12 (depends on 8)

The system of claim 8, wherein the core further includes circuitry to clear an indication that the value at the address was previously read upon a cache line eviction.

### Claim 13 (depends on 8)

The system of claim 8, wherein the core further includes circuitry to clear an indication that the value at the address was previously read upon a cache line invalidation.

### Claim 14 (depends on 8)

The system of claim 8, wherein the core further includes circuitry to:
receive a previous attempt to read the value at the address;
set an indication that the value at the address was previously read based on the previous attempt; and
use the indication to determine whether the value at the address was previously read for execution of the attempted read.

### Claim 15

A method, comprising:
receiving an instruction to monitor execution of a thread;
decoding the instruction;
scheduling the instruction;
retiring the instruction; and
based on execution of the instruction:
monitoring execution of the thread;
identifying an attempted read of an address during execution of the thread;
determining whether a value at the address was previously read during monitoring of the execution of the thread;
logging the attempted read based on a determination that the value at the address was previously read during monitoring of the execution of the thread; and
omitting logging of the attempted read based on a determination that the value at the address was not previously read during monitoring of the execution of the thread.

### Claim 16 (depends on 15)

The method of claim 15, further comprising determine whether the value at the address was previously read by tracking metadata in a cache associated with the address.

### Claim 17 (depends on 15)

The method of claim 15, further comprising determine whether the value at the address was previously read by tracking metadata in a fill buffer associated with the address.

### Claim 18 (depends on 15)

The method of claim 15, further comprising logging additional attempted accesses of memory necessary to reconstruct a trace of execution.

### Claim 19 (depends on 15)

The method of claim 15, further comprising clearing an indication that the value at the address was previously read upon a cache line eviction.

### Claim 20 (depends on 15)

The method of claim 15, further comprising clearing an indication that the value at the address was previously read upon a cache line invalidation.