# US 2017/0285996 A1 · Method for performing data updates

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- Number: US 2017/0285996 A1
- Document ID: US20170285996A1
- Status: Published application
- Kind: A1
- Application number: 15/084,440
- Filed: 2016-03-29
- Published: 2017-10-05
- Earliest claimed: 2016-03-29
- Assignees: NXP B.V.
- Applicants: NXP B.V.
- Inventors: SÖNKE OSTERTUN; Wolfgang STIDL; Raffaele COSTA
- Web page: https://patentgrep.com/patent/US20170285996A1

## CPC

- G06F 3/0632: {by initialisation or re-initialisation of storage systems}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0644: {Management of space entities, e.g. partitions, extents, pools}
- G06F 3/0653: {Monitoring storage devices or systems}
- G06F 3/0685: {Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays}
- G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/1009: using page tables, e.g. page table structures
- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc
- G06F 2212/2022: Flash memory
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G06F 2212/7204: Capacity control, e.g. partitioning, end-of-life degradation
- G06F 2212/7209: Validity control, e.g. using flags, time stamps or sequence numbers
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

In an embodiment, a method for re-programming memory is disclosed. In the embodiment, the method involves selecting a memory page based on version information and re-programming the selected memory page using cyclic redundancy check (CRC) data for the memory page.

## Claims

### Claim 1

A method for resolving collisions resulting from tearing events when updating memory, the method comprising:
selecting a memory page from a plurality of memory pages pointing to a logical memory page based on version information;
re-programming the selected memory page; and
mapping the selected memory page to the logical memory page.

### Claim 2 (depends on 1)

The method of claim 1, wherein the memory page is further selected based on performance under a quality read operation.

### Claim 3 (depends on 1)

The method of claim 1, further comprising re-programming the selected memory page using cyclic redundancy checked (CRC) data for the memory page obtained by performing a normal read operation of the page.

### Claim 4 (depends on 3)

The method of claim 3, wherein if CRC data for the selected memory page (first memory page) cannot be obtained by a normal read operation:
selecting a second memory page from the plurality of memory pages pointing to the logical memory page; and
re-programming the second memory page using CRC data obtained by performing a normal read operation of the second memory page.

### Claim 5 (depends on 1)

The method of claim 1, wherein the selected memory page is verified with a quality read operation and, if the page cannot be verified, re-programming the memory page.

### Claim 6 (depends on 1)

The method of claim 1, wherein the method further comprises determining if a tearing event has occurred by reading data programmed to a system page before selecting the memory page.

### Claim 7 (depends on 1)

The method of claim 1, wherein a validity check is performed before re-programming the memory page.

### Claim 8 (depends on 7)

The method of claim 7, wherein the validity check is performed by evaluating a validity check flag stored in an XWORD of the memory page.

### Claim 9 (depends on 7)

The method of claim 7, wherein the validity check is performed by comparing CRC data calculated from the memory page to CRC data stored in an XWORD of the memory page.

### Claim 10

A non-transitory computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform steps including:
selecting a memory page from a plurality of memory pages pointing to a logical memory page based on version information; and
re-programming the selected memory page; and
mapping the selected memory page to the logical memory page.

### Claim 11 (depends on 10)

The non-transitory computer-readable storage medium of claim 10, wherein the memory page is further selected based on performance under a quality read operation.

### Claim 12 (depends on 10)

The non-transitory computer-readable storage medium of claim 10, wherein the memory page is selected from a plurality of physical memory pages that are mapped to the same logical memory page.

### Claim 13 (depends on 10)

The non-transitory computer-readable storage medium of claim 10, wherein the non-transitory computer-readable storage medium further comprises instructions for re-programming the selected memory page using cyclic redundancy checked data obtained by performing a normal read operation of the page.

### Claim 14 (depends on 10)

The non-transitory computer-readable storage medium of claim 10, wherein the selected memory page is verified with a quality read operation and, if the page cannot be verified, re-programming the memory page.

### Claim 15 (depends on 10)

The non-transitory computer-readable storage medium of claim 10, wherein if cyclic redundancy checked data for the selected memory page (first memory page) cannot be obtained by a normal read operation:
selecting a second memory page from the plurality of memory pages pointing to the logical memory page; and
re-programming the second memory page using cyclic redundancy checked data obtained by performing a normal read operation of the second memory page.

### Claim 16 (depends on 10)

The non-transitory computer-readable storage medium of claim 10, wherein an occurrence of a tearing event is determined by reading data programmed to a system page before selecting the memory page.

### Claim 17 (depends on 10)

The non-transitory computer-readable storage medium of claim 10, wherein a validity check is performed before re-programming the memory page.

### Claim 18 (depends on 17)

The non-transitory computer-readable storage medium of claim 17, wherein the validity check is performed by evaluating a validity check flag stored in an XWORD of the memory page.

### Claim 19 (depends on 17)

The non-transitory computer-readable storage medium of claim 17, wherein the validity check is performed by comparing CRC data calculated from the memory page to CRC data stored in an XWORD of the memory page.

### Claim 20

An integrated circuit comprising a processor and memory, the memory containing instructions that, when executed by the processor, perform steps comprising:
selecting a memory page from a plurality of memory pages pointing to a logical memory page based on version information; and
re-programming the selected memory page; and
mapping the selected memory page to the logical memory page.
