# US 2017/0285992 A1 · Memory subsystem with narrow bandwidth repeater channel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0285992 A1 - Document ID: US20170285992A1 - Status: Published application - Kind: A1 - Application number: 15/089,453 - Filed: 2016-04-01 - Published: 2017-10-05 - Earliest claimed: 2016-04-01 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Pete D VOGT - Web page: https://patentgrep.com/patent/US20170285992A1 ## CPC - G06F 13/16: for access to memory bus (G06F13/28 takes precedence) - G06F 13/1684: {using multiple buses} - G06F 13/1678: {using bus width} - G06F 13/4018: {with data-width conversion} - G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports - G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring - G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A system with memory includes a repeater architecture where memory connects to a host with one bandwidth, and repeats the channel with a lower bandwidth. A memory circuit includes a first group of signal lines to couple point-to-point between a first group of memory devices and a host device. The memory circuit includes a second group of signal lines to couple point-to-point between the first group of memory devices and a second group of memory devices. The second group of signal lines extends the memory channel to the second group of memory devices. The second group of signal lines includes fewer data signal lines than the first group of signal lines, to support a lower bandwidth than the first group of signal lines on the memory channel. ## Claims ### Claim 1 A memory circuit, comprising: a first group of signal lines to couple point-to-point as a memory channel between a first group of memory devices and a host device; a second group of signal lines to couple point-to-point between the first group of memory devices and a second group of memory devices to extend the memory channel to the second group of memory devices, wherein the second group of signal lines includes fewer data signal lines than the first group of signal lines, to support a lower bandwidth than the first group of signal lines on the memory channel; and a repeater coupled to repeat signals on the memory channel between the first group of signal lines and the second group of signal lines. ### Claim 2 (depends on 1) The memory circuit of claim 1, wherein the first group of signal lines and the second group of signal lines comprises single ended data signal lines. ### Claim 3 (depends on 1) The memory circuit of claim 1, wherein the first group of signal lines and the second group of signal lines comprises differential data signal lines. ### Claim 4 (depends on 1) The memory circuit of claim 1, wherein the second group of signal lines includes half as many data signal lines as the first group of signal lines. ### Claim 5 (depends on 1) The memory circuit of claim 1, wherein the first group of memory devices is to utilize approximately one half total bandwidth of the memory channel and the second group of memory devices is to utilize approximately one half total bandwidth of the memory channel. ### Claim 6 (depends on 1) The memory circuit of claim 1, wherein the first group of memory devices is to utilize more bandwidth than the second group of memory devices. ### Claim 7 (depends on 1) The memory circuit of claim 1, wherein the first group of memory devices comprises memory devices of a first memory module, and the second group of memory devices comprises memory devices of a second memory module. ### Claim 8 (depends on 7) The memory circuit of claim 7, wherein the first memory module comprises a dual inline memory module (DIMM) including synchronous dynamic random access memory (SDRAM) devices compliant with a dual data rate version 5 (DDR5) standard, and the second memory module comprises a DIMM including SDRAM devices compliant with a dual data rate version 5 (DDR5) standard. ### Claim 9 (depends on 7) The memory circuit of claim 7, wherein the first memory module comprises a dual inline memory module (DIMM) including synchronous dynamic random access memory (SDRAM) devices compliant with a dual data rate version 5 (DDR5) standard, and the second memory module comprises a DIMM including byte-addressable, random access nonvolatile memory devices. ### Claim 10 (depends on 9) The memory circuit of claim 9, wherein the byte-addressable, random access nonvolatile memory devices comprise three dimensional memory devices including memory cells with chalcogenide glass. ### Claim 11 A system, comprising: a memory controller circuit to control access to memory; a first memory module to couple point-to-point to the memory controller circuit via a first group of signal lines of a memory channel between the memory controller circuit and the first memory module, the first memory module including a repeater; and a second memory module to couple to the memory controller circuit through the repeater via a second group of signal lines to couple point-to-point between the first memory module the second memory module, wherein the second group of signal lines includes fewer data signal lines than the first group of signal lines, to support a lower bandwidth than the first group of signal lines on the memory channel; wherein the repeater is to repeat signals on the memory channel between the first group of signal lines and the second group of signal lines. ### Claim 12 (depends on 11) The system of claim 11, wherein the first group of signal lines and the second group of signal lines comprises single ended data signal lines. ### Claim 13 (depends on 11) The system of claim 11, wherein the first group of signal lines and the second group of signal lines comprises differential data signal lines. ### Claim 14 (depends on 11) The system of claim 11, wherein the second group of signal lines includes half as many data signal lines as the first group of signal lines. ### Claim 15 (depends on 11) The system of claim 11, wherein the first memory module is to utilize approximately one half total bandwidth of the memory channel and the second memory module is to utilize approximately one half total bandwidth of the memory channel. ### Claim 16 (depends on 11) The system of claim 11, wherein the first memory module is to utilize more bandwidth than the second memory module. ### Claim 17 (depends on 11) The system of claim 11, wherein the first memory module comprises a dual inline memory module (DIMM) including synchronous dynamic random access memory (SDRAM) devices compliant with a dual data rate version 5 (DDR5) standard, and the second memory module comprises a DIMM including SDRAM devices compliant with a dual data rate version 5 (DDR5) standard. ### Claim 18 (depends on 11) The system of claim 11, wherein the first memory module comprises a dual inline memory module (DIMM) including synchronous dynamic random access memory (SDRAM) devices compliant with a dual data rate version 5 (DDR5) standard, and the second memory module comprises a DIMM including byte-addressable, random access nonvolatile memory devices. ### Claim 19 (depends on 18) The system of claim 18, wherein the byte-addressable, random access nonvolatile memory devices comprise three dimensional memory devices including memory cells with chalcogenide glass. ### Claim 20 (depends on 11) The system of claim 11, further comprising a processor coupled to the memory controller, at least one core of the processor to execute data stored in the memory modules. ### Claim 21 (depends on 20) The system of claim 20, further comprising a network adapter coupled to exchange data between the memory modules and a remote network location. ### Claim 22 (depends on 20) The system of claim 20, further comprising a display communicatively coupled to the processor.