# US 2017/0285703 A1 · Programmable Power Management Agent

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- Number: US 2017/0285703 A1
- Document ID: US20170285703A1
- Status: Published application
- Kind: A1
- Application number: 15/623,536
- Filed: 2017-06-15
- Published: 2017-10-05
- Earliest claimed: 2015-02-28
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Israel Diamand; Asaf Rubinstein; Arik Gihon; Tal Kuzi; Tomer Ziv; Nadav Shulman
- Web page: https://patentgrep.com/patent/US20170285703A1

## CPC

- G06F 1/3296: by lowering the supply or operating voltage
- G06F 1/3228: Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
- G06F 1/324: by lowering clock frequency
- G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C)
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- Y02D 30/50: in wire-line communication networks, e.g. low power modes or reduced link rate
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.

## Claims

### Claim 1

A processor comprising:
at least one core including a first core; and
a power management agent (PMA) coupled to the first core, the PMA to include:
a static table to store a list of operations, and that includes a plurality of columns, each column to specify a corresponding flow, each flow to include a corresponding subset of the operations and each flow associated with a corresponding state of the first core;
a control register (CR) to include a plurality of storage elements, wherein each storage element corresponds to a respective operation listed in the static table, each storage element to receive one of a first value and a second value; and
execution logic, responsive to a command to place the first core into a first state, to execute each operation of a first flow for which the corresponding storage element stores the first value and to refrain from execution of each operation of the first flow for which the corresponding element stores the second value.

### Claim 2 (depends on 1)

The processor of claim 1, further including a power management unit (PMU) to determine a corresponding value to be stored in each of the storage elements of the CR.

### Claim 3 (depends on 1)

The processor of claim 1, wherein upon execution of the first subset in accordance with contents of the storage elements, the core is to transition from a sleep state to an active state.

### Claim 4 (depends on 1)

The processor of claim 1, wherein upon execution of the first subset in accordance with contents of the storage elements, the first core is to be placed into a sleep state.

### Claim 5 (depends on 1)

The processor of claim 1, wherein upon execution of the first subset in accordance with contents of the storage elements, the first core is to be in a reduced activity state.

### Claim 6 (depends on 1)

The processor of claim 1, wherein in a first pass the execution logic is to execute the first subset in accordance with first contents of the storage elements, and in a second pass to execute the first subset according to second contents of the storage elements, and wherein execution of the first pass and the second pass is equivalent to a switch in sequence of two successive operations of the first subset.

### Claim 7 (depends on 1)

The processor of claim 1, wherein a corresponding value to be stored in each of the elements of the CR is to be determined based on user input.

### Claim 8

A machine-readable medium having stored thereon data, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method comprising:
receiving a command to execute a first flow to change an operating parameter of a core of a processor, wherein the first flow is specified by a sequence stored in a static storage, the sequence to indicate an execution order of a first portion of a plurality of operations;
storing, into dynamic storage elements of a control register (CR), a modified sequence that specifies the execution order of a second portion of the plurality of operations; and
responsive to the command, executing the modified sequence according to contents of the control register instead of executing the first flow according to contents of the static storage.

### Claim 9 (depends on 8)

The machine-readable medium of claim 8, wherein upon execution of the modified sequence the core is to go into a reduced power state.

### Claim 10 (depends on 8)

The machine-readable medium of claim 8, wherein upon execution of the modified sequence the core is to go into a powered up state.

### Claim 11 (depends on 10)

The machine-readable medium of claim 10, further comprising receiving the contents of the CR from a power management unit (PMU) of the processor.

### Claim 12 (depends on 8)

The machine-readable medium of claim 8, wherein execution of the modified sequence is to result in a reset of the core after a shutdown.

### Claim 13

A processor comprising:
a first core having a power management agent (PMA), the PMA comprising:
a table to statically store a list of operations including a first subset of the list of operations, wherein upon execution of the first subset, operation of the first core is to be changed from a first state to a second state;
a control register (CR) having a plurality of storage elements, each storage element associated with a corresponding operation stored in the table, wherein the CR is to specify a second subset of the list of operations; and
execution logic to execute operations, wherein responsive to a command to place the first core into the first state, the execution logic is to execute the second subset specified by the CR and not the first subset stored in the table, wherein the execution of the second subset is to change operation of the first core from the first state to the second state; and
a power management unit (PMU) to determine a corresponding value to be stored in each of the storage elements of the CR.

### Claim 14 (depends on 13)

The processor of claim 13, wherein the first state is a powered down state and the second state is a powered up state.

### Claim 15 (depends on 13)

The processor of claim 13, wherein the first state is a powered up state and the second state is a partially powered down state.

### Claim 16 (depends on 13)

The processor of claim 13, wherein the execution logic is to execute the second subset in a first pass according to first contents of the CR, and subsequently to execute a third subset of the list of operations in a second pass according to second contents of the CR, wherein the first contents of the CR differ from the second contents of the CR.

### Claim 17 (depends on 16)

The processor of claim 16, wherein the processor is to execute the second subset followed by the third subset to produce a reversal of a sequence of two successive operations of the list of operations.

### Claim 18 (depends on 17)

The processor of claim 17, wherein the processor is to execute the second subset followed by the third subset to execute a single operation, and thereafter halt execution.