# US 2017/0285381 A1 · Array substrate and manufacturing method therefor, and display panel

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- Number: US 2017/0285381 A1
- Document ID: US20170285381A1
- Status: Published application
- Kind: A1
- Application number: 15/514,366
- Filed: 2016-03-16
- Published: 2017-10-05
- Earliest claimed: 2015-04-14
- Assignees: Boe Technology Group Co., Ltd.; Beijing Boe Display Technology Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.; Beijing Boe Display Technology Co., Ltd.
- Inventors: Xiao WANG
- Web page: https://patentgrep.com/patent/US20170285381A1

## CPC

- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- G02F 1/134309: {characterised by their geometrical arrangement}
- G02F 1/134363: {for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]}
- G02F 1/136286: {Wiring, e.g. gate line, drain line}
- H10D 84/01: Manufacture or treatment
- H10D 86/01: Manufacture or treatment
- H10D 86/021: {of multiple TFTs}
- G02F 1/134372: {for fringe field switching [FFS] where the common electrode is not patterned}
- G02F 1/13606: {having means for reducing parasitic capacitance}
- G02F 1/136218: {Shield electrodes}
- G02F 1/13629: {Multilayer wirings}
- G02F 1/136295: {Materials; Compositions; Manufacture processes}
- G02F 2201/121: common or background
- G02F 2201/123: pixel
- G02F 2202/10: semiconductor
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Provided are an array substrate and a manufacturing method therefor, and a display panel. The array substrate comprises: a base substrate; a data line and a passivation layer which are formed on the base substrate; a common electrode layer formed on the passivation layer; and a shielding electrode layer and a barrier layer which are formed on the base substrate, wherein the shielding electrode layer is arranged between the data line and the passivation layer, the barrier layer is arranged between the data line and the shielding electrode layer, the shielding electrode layer is grounded, and the barrier layer is made of a material with an insulation function.

## Claims

### Claim 1

An array substrate, comprising:
a base substrate;
a data line and a passivation layer, formed on the base substrate;
a common electrode layer, formed on the passivation layer;
a shielding electrode layer and a barrier layer, formed on the base substrate,
wherein, the shielding electrode layer is arranged between the data line and the passivation layer,
the barrier layer is arranged between the data line and the shielding electrode layer,
the shielding electrode layer is configured to be grounded, and a material of the barrier layer is an insulating material.

### Claim 2 (depends on 1)

The array substrate according to claim 1, wherein, the array substrate further comprises a pixel electrode layer formed below the passivation layer, and the shielding electrode layer and the pixel electrode layer are formed in a same layer.

### Claim 3 (depends on 2)

The array substrate according to claim 2, wherein, the shielding electrode layer and the pixel electrode layer are same in material.

### Claim 4 (depends on 1)

The array substrate according to claim 1, wherein, the array substrate further comprises a thin film transistor formed on the base substrate, and the barrier layer is further arranged on the thin film transistor and covers an active layer of the thin film transistor.

### Claim 5 (depends on 1)

The array substrate according to claim 1, wherein, the material of the barrier layer includes: silicon nitride, silicon oxynitride, silicon oxide or an organic film.

### Claim 6 (depends on 1)

The array substrate according to claim 1, wherein, a thickness of the barrier layer is 1000-6000 Å.

### Claim 7 (depends on 6)

The array substrate according to claim 6, wherein, the thickness of the barrier layer is 200 Å.

### Claim 8 (depends on 1)

The array substrate according to claim 1, wherein, a thickness of the shielding electrode layer is 300-700 Å.

### Claim 9

A manufacturing method of an array substrate, comprising:
forming a data line and a passivation layer on a base substrate;
forming a common electrode layer on the passivation layer;
forming a shielding electrode layer between the data line and the passivation layer;
forming a first barrier layer between the data line and the shielding electrode layer;
wherein, the shielding electrode layer is configured to be grounded, and a material of the first barrier layer is an insulating material.

### Claim 10 (depends on 9)

The method according to claim 9, further comprising;
forming a pixel electrode layer below the passivation layer;
forming the shielding electrode layer on the data line includes:
forming the shielding electrode layer on the data line and in a same layer with the pixel electrode layer, by using a material same as that of the pixel electrode layer.

### Claim 11 (depends on 9)

The method according to claim 9, further comprising;
forming a thin film transistor on the base substrate;
forming a second barrier layer on the thin film transistor and covering an active layer of the thin film transistor;
wherein, the first barrier layer and the second barrier layer are formed by a same material and in a same layer.

### Claim 12 (depends on 9)

The method according to claim 9, wherein, the material of the barrier layer includes: silicon nitride, silicon oxynitride, silicon oxide or an organic film.

### Claim 13 (depends on 1)

A display panel, wherein, the display panel comprises the array substrate according to claim 1.