# US 2017/0285380 A1 · Array substrate and semiconductor device containing the same, and method for fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0285380 A1 - Document ID: US20170285380A1 - Status: Published application - Kind: A1 - Application number: 15/509,281 - Filed: 2016-10-10 - Published: 2017-10-05 - Earliest claimed: 2015-10-10 - Assignees: Boe Technology Group Co., Ltd.; Hefei Xinsheng Optoelectronics Technology Co., Ltd. - Applicants: Boe Technology Group Co., Ltd; Hefei Xinsheng Optoelectronics Technology Co. Ltd. - Inventors: Jideng ZHOU - Web page: https://patentgrep.com/patent/US20170285380A1 ## CPC - G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} - G02F 1/134309: {characterised by their geometrical arrangement} - G02F 1/134336: {Matrix} - G02F 1/13439: {characterised by their electrical, optical, physical properties; materials therefor; method of making} - G02F 1/136213: {Storage capacitors associated with the pixel electrode} - G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer} - G02F 1/136286: {Wiring, e.g. gate line, drain line} - G02F 1/133707: {Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes} - G02F 1/133753: {with different alignment orientations or pretilt angles on a same surface, e.g. for grey scale or improved viewing angle} - G02F 1/134345: {Subdivided pixels, e.g. for grey scale or redundancy} - G02F 1/134363: {for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]} - G02F 1/136295: {Materials; Compositions; Manufacture processes} - G02F 2201/121: common or background - G02F 2201/122: having a particular pattern - G02F 2201/123: pixel - G02F 2203/01: transmissive - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors} - H10D 86/60: wherein the TFTs are in active matrices - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract The present disclosure provides an array substrate. The array substrate includes a substrate having a display region with a plurality of pixel regions, each pixel region having two or more first regions; a common electrode line between two adjacent pixel regions; a gate line; a data line intersecting with the gate line; at least one of the gate line and the data line being in a second region between two adjacent first regions; and a pixel electrode having a hollowed-out pattern within a corresponding first region, pixel electrodes corresponding to the two or more first regions being a pixel electrode unit. ## Claims ### Claim at position 1 1-20. (canceled) ### Claim 21 An array substrate, comprising: a substrate having a display region with a plurality of pixel regions, each pixel region having two or more first regions; a common electrode line between two adjacent pixel regions; a gate line; a data line intersecting with the gate line; at least one of the gate line and the data line being in a second region between two adjacent first regions; and a pixel electrode having a hollowed-out pattern within a corresponding first region, pixel electrodes corresponding to the two or more first regions being a pixel electrode unit. ### Claim 22 (depends on 21) The array substrate according to claim 21, wherein: each pixel electrode corresponds to a first region, and an area of the pixel electrode corresponds to an area of the first region. ### Claim 23 (depends on 21) The array substrate according to claim 21, further comprising: a first insulating layer being between the gate line and the data line; and a second insulating layer being between the data line and the pixel electrode unit. ### Claim 24 (depends on 21) The array substrate according to claim 21, wherein: a pixel region includes four first regions arranged in a two by two configuration; and the gate line and the data line are in the second region being perpendicular to each other. ### Claim 25 (depends on 24) The array substrate according to claim 24, wherein: hollowed-out patterns of two adjacent pixel electrodes are axisymmetric. ### Claim 26 (depends on 21) The array substrate according to claim 21, wherein: the hollowed-out pattern includes one or more of slit shapes and stripe shapes. ### Claim 27 (depends on 22) The array substrate according to claim 22, further comprising a thin-film transistor, the thin-film transistor comprising: a gate electrode being integrated with the gate line; first electrodes being electrically connected to the pixel electrode; a second electrode being integrated with the data line; an active layer being electrically connected to the first electrodes and the second electrode, wherein: the data line, the common electrode line, and first electrodes are over the gate electrode, the data line, the common electrode line, and the first electrodes being separated from the gate electrode by a first insulating layer; the gate electrode and the gate line are on the substrate; the active layer is on the gate electrode and is separated from the gate electrode by the first insulating layer, the active layer being electrically connected with the first electrodes and the second electrode; the second electrode of and the data line are one piece; and the pixel electrode unit is over the data line, the pixel electrode unit being connected to the first electrodes through first via holes, the first via holes being through the second insulating layer. ### Claim 28 (depends on 27) The array substrate according to claim 27, further comprising: a third insulating layer being between the second insulating layer and the pixel electrode; a first via holes being through the second insulating layer and the third insulating layer, wherein: the pixel electrode being connected to the first electrodes through the first via hole. ### Claim 29 (depends on 28) The array substrate according to claim 28, wherein the third insulating layer is made of an organic insulating material. ### Claim 30 (depends on 21) The array substrate according to claim 21, further comprising a storage electrode formed in areas corresponding to the common electrode line, wherein: the first insulating layer is between the storage electrode and the common electrode line; and the storage electrode is electrically connected to the pixel electrode and forms a storage capacitor structure with the common electrode line. ### Claim 31 (depends on 30) The array substrate according to claim 30, wherein: the storage electrode is integrated with the gate line. ### Claim 32 (depends on 31) The array substrate according to claim 31, wherein: at least one common electrode line substantially overlaps with the pixel electrode; and the second insulating layer is between the common electrode line and the pixel electrode. ### Claim 33 (depends on 21) The array substrate according to claim 21, wherein the pixel electrode is of a squared shape. ### Claim 34 (depends on 21) A semiconductor device, comprising the array substrate according to claim 21. ### Claim 35 (depends on 34) The semiconductor device according to claim 34, further comprising: a cover substrate with a clear region corresponding to the pixel electrode for improving light transmittance. ### Claim 36 A method for fabricating an array substrate, comprising: providing a substrate having a display region with a plurality of pixel regions, each pixel region having two or more first regions, and a second region between two adjacent first regions; forming a gate line and a gate electrode of a thin-film transistor on a substrate, the gate line and the gate electrode of the thin-film transistor being formed in a same fabrication step; forming a first insulating layer; forming an active layer of the thin-film transistor, the active layer being located in an area where the gate line and a data line intersect; forming a data line, common electrode lines between two adjacent pixel regions, first electrodes, and a second electrode, at least one of the gate line and the data line being formed in the second region; forming a second insulating layer and first via holes, the first via holes being through the second insulating layer; and forming a pixel electrode with a hollowed-out pattern in the pixel region being connected to the first electrodes through the first via holes, the hollowed-out pattern corresponding to the first region. ### Claim 37 (depends on 36) The method according to claim 36, wherein: the hollowed-out pattern having one or more of slit shapes and stripe shapes; each pixel region includes four first regions arranged in a two by two configuration; and the gate line and the data line being perpendicular to each other are fabricated in the second region. ### Claim 38 (depends on 36) The method according to claim 36, further comprising: forming a third insulating layer on the second insulating layer, the first via holes being through the third insulating layer and the second insulating layer. ### Claim 39 (depends on 36) The method according to claim 36, further comprising: forming storage electrodes in areas corresponding to the common electrode lines, the storage electrodes and the gate line being formed in a same fabrication step; and forming second via holes in areas corresponding to the storage electrodes, the second via holes and the second insulating layer being formed in a same fabrication step, the second via holes being through the first insulating layer and the second insulating layer, and the pixel electrode being connected to the storage electrodes through the second via holes. ### Claim 40 (depends on 36) The method according to claim 36, wherein the pixel electrode unit overlaps with at least one common electrode line.