# US 2017/0285104 A1 · Identification of unknown sources for logic built-in self test in verification

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- Number: US 2017/0285104 A1
- Document ID: US20170285104A1
- Status: Published application
- Kind: A1
- Application number: 15/628,880
- Filed: 2017-06-21
- Published: 2017-10-05
- Earliest claimed: 2014-12-19
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Satya R. S. Bhamidipati; Mary P. Kusko; Cedric Lichtenau; Srinivas V. N. Polisetty
- Web page: https://patentgrep.com/patent/US20170285104A1

## CPC

- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/31724: {Test controller, e.g. BIST state machine (for scan test G01R31/318555)}
- G06F 11/00: Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00)
- G06F 11/27: Built-in tests
- G06F 30/30: Circuit design
- G06F 30/33: Design verification, e.g. functional simulation or model checking
- G06F 30/3308: using simulation
- G06F 30/333: Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A tool for determining unknown sources in a circuit design for exclusion from logic built-in self test (LBIST) verification for the circuit. Responsive to initializing each of one or more latches in one or more test channels of the circuit design being tested, the tool determines whether a latch of the one or more latches is corrupted by an unknown source. The tool gathers each of the one or more latches determined to be an unknown source after a capture clock phase. The tool performs a backward traverse of logic circuitry feeding each of the one or more latches determined to be an unknown source. The tool verifies that a fence on one or more unknown source nets associated with each of the one or more latches blocked the unknown source from contributing to a test signature.

## Claims

### Claim 1

A method for determining unknown sources in a circuit design for exclusion from logic built-in self test (LBIST) verification for the circuit, the method comprising:
responsive to initializing each of one or more latches in one or more test channels of the circuit design being tested, determining, by one or more computer processors, whether a latch of the one or more latches is corrupted by an unknown source;
gathering, by one or more computer processors, each of the one or more latches determined to be an unknown source after a capture clock phase;
performing, by one or more computer processors, a backward traverse of logic circuitry feeding each of the one or more latches determined to be an unknown source; and
verifying, by one or more computer processors, that a fence on one or more unknown source nets associated with each of the one or more latches blocked the unknown source from contributing to a test signature.

### Claim 2 (depends on 1)

The method of claim 1 further comprises:
determining, by one or more computer processors, an initial nets list, wherein determining the initial nets list includes collecting each of one or more nets within the circuit design being tested, wherein the one or more nets include both known sources and unknown sources.

### Claim 3 (depends on 1)

The method of claim 1 further comprises:
initializing, by one or more computer processors, one or more nets contained in an initial nets list; and
configuring, by one or more computer processors, each of the one or more nets as an unknown source.

### Claim 4 (depends on 1)

The method of claim 1 further comprises:
determining, by one or more computer processors, a second nets list, wherein determining the second nets list includes collecting each of one or more nets that are free of unknown sources; and
removing, by one or more computer processors, each of the one or more nets that are free of unknown sources from the initial nets list to avoid consideration of those known sources during unknown source detection.

### Claim 5 (depends on 4)

The method of claim 4 further comprises:
configuring, by one or more computer processors, test logic circuitry to operate within a desired test mode;
configuring, by one or more computer processors, one or more fences designed to block unknown sources, such that an output of the one or more fences is free of unknown sources; and
collecting, by one or more computer processors, each of the one or more nets that is the output of the one or more fences.

### Claim 6 (depends on 1)

The method of claim 1 further comprises:
removing, by one or more computer processors, one or more nets initialized in response to initialization of each of one or more latches in one or more test channels; and
initializing, by one or more computer processors, each of the one or more latches in the one or more test channels.

### Claim 7 (depends on 1)

The method of claim 1, wherein determining that a latch of the one or more latches is corrupted by an unknown source, further comprises:
initializing, by one or more computer processors, all of one or more nets in an initial nets list, and setting the one or more nets to unknown sources prior to a capture phase of LBIST testing.

### Claim 8 (depends on 1)

The method of claim 1 further comprises:
responsive to determining that a latch of the one or more latches is corrupted by the unknown source, initiating, by one or more computer processors, a circuit design element to block the unknown source.

### Claim 9 (depends on 1)

The method of claim 1, wherein verifying that a fence on one or more unknown source nets associated with each of the one or more latches blocked the unknown source from contributing to a test signature, further comprises:
determining, by one or more computer processors, the one or more unknown source nets and one or more fence locations for each of the one or more latches determined to be an unknown source; and
blocking, by one or more computer processors, each of the one or more latches by using the fence on the one or more unknown source nets associated with each of the one or more latches.

### Claim 10

A computer system for determining unknown sources in a circuit design for exclusion from logic built-in self test (LBIST) verification for the circuit, the computer system comprising:
one or more computer processors;
one or more computer readable storage media;
program instructions stored on at least one of the one or more computer readable storage media for execution by at least one of the one or more computer processors, the program instructions comprising:
responsive to initializing each of one or more latches in one or more test channels of the circuit design being tested, program instructions to determine whether a latch of the one or more latches is corrupted by an unknown source;
program instructions to gather each of the one or more latches determined to be an unknown source after a capture clock phase;
program instructions to perform a backward traverse of logic circuitry feeding each of the one or more latches determined to be an unknown source; and
program instructions to verify that a fence on one or more unknown source nets associated with each of the one or more latches blocked the unknown source from contributing to a test signature.

### Claim 11 (depends on 10)

The computer system of claim 10 further comprises:
program instructions to determining, by one or more computer processors, an initial nets list, wherein determining the initial nets list includes collecting each of one or more nets within the circuit design being tested, wherein the one or more nets include both known sources and unknown sources.

### Claim 12 (depends on 10)

The computer system of claim 10 further comprises:
program instructions to initialize one or more nets contained in an initial nets list; and
program instructions to configure each of the one or more nets as an unknown source.

### Claim 13 (depends on 10)

The computer system of claim 10 further comprises:
program instructions to determine a second nets list, wherein determining the second nets list includes collecting each of one or more nets that are free of unknown sources; and
program instructions to remove each of the one or more nets that are free of unknown sources from the initial nets list to avoid consideration of those known sources during unknown source detection.

### Claim 14 (depends on 13)

The computer system of claim 13 further comprises:
program instructions to configure test logic circuitry to operate within a desired test mode;
program instructions to configure one or more fences designed to block unknown sources, such that an output of the one or more fences is free of unknown sources; and
program instructions to collect each of the one or more nets that is the output of the one or more fences.

### Claim 15 (depends on 10)

The computer system of claim 10 further comprises:
program instructions to remove one or more nets initialized in response to initialization of each of one or more latches in one or more test channels; and
initializing, by one or more computer processors, each of the one or more latches in the one or more test channels.

### Claim 16 (depends on 10)

The computer system of claim 10, wherein program instructions to determine that a latch of the one or more latches is corrupted by an unknown source, further comprises:
program instructions to initialize all of one or more nets in an initial nets list, and setting the one or more nets to unknown sources prior to a capture phase of LBIST testing.

### Claim 17 (depends on 10)

The computer system of claim 10 further comprises:
responsive to determining that a latch of the one or more latches is corrupted by the unknown source, program instructions to initiate a circuit design element to block the unknown source.

### Claim 18 (depends on 10)

The computer system of claim 10, wherein program instructions to verify that a fence on one or more unknown source nets associated with each of the one or more latches blocked the unknown source from contributing to a test signature, further comprises:
program instructions to determine the one or more unknown source nets and one or more fence locations for each of the one or more latches determined to be an unknown source; and
program instructions to block each of the one or more latches by using the fence on the one or more unknown source nets associated with each of the one or more latches.

### Claim 19

A computer program product for determining unknown sources in a circuit design for exclusion from logic built-in self test (LBIST) verification for the circuit, the computer program product comprising:
one or more computer readable storage media and program instructions stored on the one or more computer readable storage media, the program instructions comprising:
responsive to initializing each of one or more latches in one or more test channels of the circuit design being tested, program instructions to determine whether a latch of the one or more latches is corrupted by an unknown source;
program instructions to gather each of the one or more latches determined to be an unknown source after a capture clock phase;
program instructions to perform a backward traverse of logic circuitry feeding each of the one or more latches determined to be an unknown source; and
program instructions to verify that a fence on one or more unknown source nets associated with each of the one or more latches blocked the unknown source from contributing to a test signature.

### Claim 20 (depends on 19)

The computer program product of claim 19 further comprises:
responsive to determining that a latch of the one or more latches is corrupted by an unknown source, program instructions to initiate a circuit design element to block the unknown source.
