# US 2017/0285103 A1 · Scan testing using scan frames with embedded commands

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- Number: US 2017/0285103 A1
- Document ID: US20170285103A1
- Status: Published application
- Kind: A1
- Application number: 15/622,840
- Filed: 2017-06-14
- Published: 2017-10-05
- Earliest claimed: 2006-02-03
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Lee D. Whetsel
- Web page: https://patentgrep.com/patent/US20170285103A1

## CPC

- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/3172: {Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing}
- G01R 31/31723: {Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926)}
- G01R 31/31725: {Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937)}
- G01R 31/31727: {Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922)}
- G01R 31/318536: {Scan chain arrangements, e.g. connections, test bus, analog signals}
- G01R 31/318572: {Input/Output interfaces}
- G01R 31/318577: {AC testing, e.g. current testing, burn-in}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

## Claims

### Claim 1

An integrated circuit comprising:
(a) logic circuitry;
(b) parallel scan paths coupled to the logic circuitry, each scan path having a scan input and a scan output;
(c) a differential data input buffer having differential inputs and an output;
(d) a differential data output buffer having an input and differential outputs;
(e) a differential clock input buffer having differential inputs and a clock output;
(f) stimulus data circuitry having a serial input coupled to the output of the differential data input buffer, control inputs, a serial output, and parallel outputs coupled with the scan inputs of the parallel scan paths;
(g) header data circuitry having a serial input connected with the serial output of the stimulus data circuitry, control inputs, and a command output;
(h) response data circuitry having parallel inputs coupled with the scan outputs, control inputs, a serial input, and a serial output coupled with the input of the differential data output buffer;
(i) header return circuitry having an input connected with the command output of the header data circuitry, control inputs, and a serial output connected with the serial input of the response data circuitry; and
(j) controller circuitry having control outputs connected with the control inputs of the scan paths, the stimulus data circuitry, the header data circuitry, the response data circuitry, and the header return circuitry, a clock input coupled with the clock output of the differential clock input buffer, and a command input connected with the command output of the header data circuitry.

### Claim 2 (depends on 1)

The integrated circuit of claim 1 in which the header data circuitry has a second output and the test controller has a second input connected with the second output of the header data circuitry.

### Claim 3 (depends on 1)

The integrated circuit of claim 1 in which the header data circuitry has a second output and the header return circuitry has a second input connected with the second output of the header data circuitry.

### Claim 4 (depends on 1)

The integrated circuit of claim 1 in which the control outputs include a serial scan enable lead, a parallel scan enable lead, and a scan clock lead.

### Claim 5 (depends on 1)

The integrated circuit of claim 1 in which the scan paths include shift elements connected in series and each shift element includes a multiplexer and a flip-flop.

### Claim 6 (depends on 1)

The integrated circuit of claim 1 in which the stimulus data circuitry includes shift elements connected in series and each shift element includes a multiplexer and a flip-flop.

### Claim 7 (depends on 1)

The integrated circuit of claim 1 in which the response data circuitry includes shift elements connected in series and each shift element includes a multiplexer and a flip-flop.

### Claim 8 (depends on 1)

The integrated circuit of claim 1 in which the header data circuitry includes shift elements connected in series and each shift element includes a multiplexer and a flip-flop.

### Claim 9 (depends on 1)

The integrated circuit of claim 1 in which the header return circuitry includes shift elements connected in series and each shift element includes a multiplexer and a flip-flop.