# US 2017/0285099 A1 · Method and system for predicting high-temperature operating life of sram devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0285099 A1 - Document ID: US20170285099A1 - Status: Published application - Kind: A1 - Application number: 15/348,669 - Filed: 2016-11-10 - Published: 2017-10-05 - Earliest claimed: 2016-03-31 - Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation - Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation - Inventors: Wei-Ting CHIEN; Yueqin ZHU; Yongliang SONG; Yong ZHAO - Web page: https://patentgrep.com/patent/US20170285099A1 ## CPC - G01R 31/2875: {related to heating} - G01R 31/2642: {Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests} - G01R 31/2856: {Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]} - G11C 29/006: {at wafer scale level, i.e. wafer scale integration [WSI]} - G11C 29/06: Acceleration testing - G11C 29/50004: {of threshold voltage} - G11C 29/50012: {of timing} - G11C 29/50016: {of retention} - G11C 29/56008: {Error analysis, representation of errors} - G01R 31/2831: {Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates (G01R31/318511 takes precedence; testing during manufacture H10P74/00)} - G11C 11/412: using field-effect transistors only - G11C 2029/0403: {during or with feedback to manufacture} - G11C 2029/4002: {Comparison of products, i.e. test results of chips or with golden chip} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A method for predicting high-temperature operating life of an integrated circuit (IC) includes performing bias temperature instability tests and high-temperature operating life tests on a device of the IC, establishing a relationship between the device bias temperature instability and the IC's high-temperature operating life based on a result of the bias temperature instability tests and the high-temperature operating life tests. The method further includes providing a lot of subsequent integrated circuits (ICs), performing wafer-level bias temperature instability tests on a device of the ICs, and predicting high-temperature operating life of the ICs based on a result of the wafer-level bias temperature instability tests and based on the established relationship between the device's bias temperature instability and the IC's high-temperature operating life. The method can save significant effort and time over conventional approaches for accurate prediction of high-temperature operating life of an IC. ## Claims ### Claim 1 A method for predicting a high-temperature operating life, the method comprising: providing an integrated circuit (IC) including a plurality of first devices; performing bias temperature instability tests on a first device of the plurality of first devices; performing high-temperature operating life tests on the IC; establishing a relationship between the first device's bias temperature instability and the IC's high-temperature operating life based on a result of the bias temperature instability tests and the high-temperature operating life tests; providing a lot of subsequent integrated circuits (ICs) each including a plurality of second devices; performing wafer-level bias temperature instability tests on a second device of the plurality of second devices; and predicting high-temperature operating life of the lot of subsequent ICs based on a result of the wafer-level bias temperature instability tests and based on the relationship between the first device's bias temperature instability and the IC's high-temperature operating life. ### Claim 2 (depends on 1) The method of claim 1, wherein the high-temperature operating life tests comprise testing a change of a minimum operating voltage of the IC over time. ### Claim 3 (depends on 2) The method of claim 2, wherein the IC is a static random access memory (SRAM) device, and the high-temperature operating life tests comprise testing a minimum read operating voltage of the SRAM device. ### Claim 4 (depends on 3) The method of claim 3, wherein the first device is a pull-down transistor of the SRAM device. ### Claim 5 (depends on 4) The method of claim 4, wherein performing the bias temperature instability tests comprises positive bias temperature instability tests of the pull-down transistor. ### Claim 6 (depends on 5) The method of claim 5, wherein performing the bias temperature instability tests comprises testing a change of a threshold voltage of the pull-down transistor over time. ### Claim 7 (depends on 6) The method of claim 6, wherein the relationship between the first device's bias temperature instability and the IC's high-temperature operating life represents a relationship between a threshold voltage degradation of a single device in a memory device and a minimum read operating voltage degradation of the memory device. ### Claim 8 (depends on 1) The method of claim 1, wherein the bias temperature instability tests and the high-temperature operating life tests are performed under a same stress condition. ### Claim 9 An apparatus for predicting high-temperature operating life of an integrated circuit (IC) comprising a plurality of first devices, the apparatus comprising: a first test unit configured to perform bias temperature instability tests on a first device of the plurality of first devices and high-temperature operating life tests of the IC; an analyzing unit configured to establish a relationship between the first device's bias temperature instability and the IC's high-temperature operating life based on a result of the bias temperature instability tests and the high-temperature operating life tests; a second test unit configured to perform wafer-level bias temperature instability tests on a second device of a lot of subsequent integrated circuits (ICs) each comprising a plurality of second devices; and a prediction unit configured to predict high-temperature operating life of the subsequent ICs based on a result of the wafer-level bias temperature instability tests and the relationship between the first device's bias temperature instability and the IC's high-temperature operating life. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the high-temperature operating life tests comprise testing a change of a minimum operating voltage of the IC over time. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein the IC is a static random access memory (SRAM) device, and the high-temperature operating life tests comprise testing a minimum read operating voltage of the SRAM device. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein the first device is a pull-down transistor of the SRAM device. ### Claim 13 (depends on 12) The apparatus of claim 12, wherein the first test unit is configured to perform positive bias temperature instability tests of the pull-down transistor. ### Claim 14 (depends on 13) The apparatus of claim 13, wherein the first test unit is configured to test a change of a threshold voltage of the pull-down transistor over time. ### Claim 15 (depends on 14) The apparatus of claim 14, wherein the established relationship between the first device's bias temperature instability and the IC's high-temperature operating life represents a relationship between a threshold voltage degradation of a single device in a memory device and a minimum read operating voltage degradation of the memory device. ### Claim 16 (depends on 9) The apparatus of claim 9, wherein the first test unit performs the bias temperature instability tests and the high-temperature operating life tests under a same stress condition.