# US 2017/0257946 A1 · Method for fabricating ceramic insulator for electronic packaging

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- Number: US 2017/0257946 A1
- Document ID: US20170257946A1
- Status: Published application
- Kind: A1
- Application number: 15/602,137
- Filed: 2017-05-23
- Published: 2017-09-07
- Earliest claimed: 2015-11-10
- Assignees: He Bei Sinopack Electronic Tech Co., Ltd.
- Applicants: He Bei Sinopack Electronic Tech Co., Ltd.
- Inventors: Dongliang Zhao; Fei Ding; Linjie Liu
- Web page: https://patentgrep.com/patent/US20170257946A1

## CPC

- H05K 1/0306: {Inorganic insulating substrates, e.g. ceramic, glass}
- H05K 1/0213: {Electrical arrangements not otherwise provided for}
- H05K 1/0243: {Printed circuits associated with mounted high frequency components}
- H05K 1/0298: {Multilayer circuits}
- H05K 1/112: {directly combined with via connections}
- H05K 3/005: {Punching of holes}
- H05K 3/188: {by direct electroplating}
- H05K 3/40: Forming printed elements for providing electric connections to or between printed circuits
- H05K 3/4038: {Through-connections; Vertical interconnect access [VIA] connections (H05K3/403, H05K3/42 take precedence)}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/685: comprising multiple insulating layers
- H10W 70/692: Ceramics or glasses
- H05K 3/4617: {characterized by laminating only or mainly similar single-sided circuit boards}
- H05K 2201/0723: provided by an inner layer of PCB
- H05K 2201/09218: Conductive traces
- H05K 2201/09618: Via fence, i.e. one-dimensional array of vias
- H05K 2201/10303: Pin-in-hole mounted pins
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/68: Shapes or dispositions thereof
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present application discloses a method for fabricating ceramic insulator for electronic packaging, and relates to a technical field of outer shell packaging of electronic devices. Under the circumstance of using neither a chemical coating nor any bonding wire connection circuit, through a design that builds a electroplated circuit into the ceramic insulator, the method accomplishes coating of a nickel alloy protection layer onto a porcelain by an electroplating method, so that not only quality of a coating layer but also requirement of a complete appearance can be ensured. All circuits of the ceramic insulator fabricated by the aforesaid method can conduct with external circuits, such that the electroplating method can be used to accomplish coating of the nickel alloy layer, after accomplishment of all metal coating, metallization parts on an end surface of the porcelain is removed.

## Claims

### Claim 1

A method for fabricating a ceramic insulator for electronic packaging, comprising following steps:
first, punching holes at positions of bonding pads of a first ceramic layer of a ceramic insulator, metallizing and solidifying the holes, afterwards, printing an upper electric control layer circuit, the upper electric control layer circuit comprises a plurality of metal strips, the metal strips are insulated from and not interconnected with each other, but the metal strips correspond to metal in the holes one to one, and are interconnected with the metal in the holes;
second, using an underside of the first ceramic layer as a second ceramic layer, punching two groups of holes respectively on two sides of the second ceramic layer corresponding to the holes of the first ceramic layer, metallizing and solidifying the holes of the second ceramic layer, such that the total number of the holes at the two sides of the second ceramic layer is equal to the number of the holes at the first ceramic layer;
third, printing an upper electroplating circuit layer on an upper surface of the second ceramic layer, the upper electroplating circuit layer comprises a plurality of metal strips, via the printed metal strips, connecting metal in the holes at the two sides of the second ceramic layer one to one with corresponding metal in the holes at the first ceramic layer, the metal strips on the upper surface of the second ceramic layer are insulated from and not interconnected with each other;
four, an underside of the second ceramic layer being provided with an intermediate ceramic component layer, punching holes on two sides of the intermediate ceramic component layer, metallizing and solidifying the holes, such that positions and the number of the holes at the intermediate ceramic component layer correspond to that of the holes at the second ceramic layer;
five, an underside of the intermediate ceramic component layer being provided with a third ceramic layer, printing a lower electroplating circuit layer on an upper surface of the third ceramic layer, the lower electrodesposition circuit layer comprises a plurality of metal strips, the metal strips are insulated from and not interconnected with each other; connecting the printed metal strips one to one with corresponding metal in the holes of the intermediate ceramic component layer, and making one end of each of the metal strips on the third ceramic layer extend to an edge of the third ceramic layer to form a leading-out terminal, such that electric connections between the third metal strips and device(s) at the exterior of the porcelain can be realized, via the aforesaid steps, forming a built-in electroplating circuit of a raw porcelain.

### Claim 2 (depends on 1)

The method for fabricating the ceramic insulator for electronic packaging according to claim 1, wherein: the intermediate ceramic component layer comprises a fourth ceramic layer, a fifth ceramic layer and a sixth ceramic layer, an upper surface of the fourth ceramic layer is provided with an upper GND layer, an upper surface of the fifth ceramic layer is provided with an RF layer, an upper surface of the sixth ceramic layer is provided with a lower GND layer, the upper GND layer, the RF layer and the lower GND layer are insulated from and not interconnected with the third connecting metal wires.

### Claim 3 (depends on 2)

The method for fabricating the ceramic insulator for electronic packaging according to claim 2, wherein: the RF layer comprises a plurality of metal strips, two ends of each of the metal strips extend to an outer side of the fifth ceramic layer to form leading-out terminals, such that electric connections between the metal strips and device(s) at the exterior of the porcelain can be realized; each of the upper GND layer and the lower GND layer comprises a piece of metal electrode, the metal electrodes are interconnected with the GND metal strips in the RF layer by means of metallization of the interlayer via holes, such that the upper GND layer and the lower GND layer can be electrically connected with the GND circuits of the RF layer.

### Claim 4 (depends on 3)

The method for fabricating the ceramic insulator for electronic packaging according to claim 3, further comprising a step of metallizing the leading-out terminal of the raw porcelain.

### Claim 5 (depends on 4)

The method for fabricating the ceramic insulator for electronic packaging according to claim 4, further comprising a sintering step after the step of metallizing the leading-out terminal, which is configured for sintering the raw porcelain into a ripe porcelain.