# US 2017/0257589 A1 · Control device, control method, and solid-state imaging device

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- Number: US 2017/0257589 A1
- Document ID: US20170257589A1
- Status: Published application
- Kind: A1
- Application number: 15/503,106
- Filed: 2015-08-14
- Published: 2017-09-07
- Earliest claimed: 2014-08-26
- Assignees: Sony Semiconductor Solutions Corporation
- Applicants: Sony Semiconductor Solutions Corporation
- Inventors: Tomoyasu TATE
- Web page: https://patentgrep.com/patent/US20170257589A1

## CPC

- H04N 25/779: Circuitry for scanning or addressing the pixel array
- H04N 25/532: by controlling global shutters in CMOS SSIS
- H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
- H04N 25/76: Addressed sensors, e.g. MOS or CMOS sensors
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

The present disclosure relates to a control device, a control method, and a solid-state imaging device that enable a larger number of shutter row addresses to be set at the same time. A vertical selection decoder and a latch circuit set shutter row addresses that identify rows of pixels for which an electronic shutter operation is performed, of pixels arranged in a matrix manner, on the basis of a start address and an end address of the shutter row addresses. The present disclosure is applicable to, for example, a CMOS image sensor that sets the shutter row addresses.

## Claims

### Claim 1

A control device comprising:
an address setting unit configured to set shutter row addresses that identify rows of pixels for which an electronic shutter operation is performed, of pixels arranged in a matrix manner, on the basis of a start address and an end address of the shutter row addresses.

### Claim 2 (depends on 1)

The control device according to claim 1, wherein the address setting unit is configured to set a reading row address that identifies a row of pixels from which a pixel signal is read, of the pixels arranged in a matrix manner, on the basis of a start address and an end address of the reading row address.

### Claim 3 (depends on 1)

The control device according to claim 1, wherein the address setting unit is configured to set the shutter row addresses on the basis of the start address, the end address, and a signal that makes simultaneous generation of a plurality of addresses valid.

### Claim 4 (depends on 1)

The control device according to claim 1, wherein the address setting unit is configured to set the shutter row addresses other than an invalid shutter row address that identifies a row of pixels for which the electronic shutter operation is made invalid, of rows identified by the shutter row addresses, on the basis of the invalid shutter row address, the start address, and the end address.

### Claim 5

A control method comprising:
an address setting step of setting, by a control device, shutter row addresses that identify rows of pixels for which an electronic shutter operation is performed, of pixels arranged in a matrix manner, on the basis of a start address and an end address of the shutter row addresses.

### Claim 6

A solid-state imaging device comprising:
pixels arranged in a matrix manner; and
an address setting unit configured to set shutter row addresses that identify rows of pixels for which an electronic shutter operation is performed, of the pixels arranged in a matrix manner, on the basis of a start address and an end address of the shutter row addresses.