# US 2017/0257104 A1 · Method for robust phase-locked loop design

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- Number: US 2017/0257104 A1
- Document ID: US20170257104A1
- Status: Published application
- Kind: A1
- Application number: 15/428,059
- Filed: 2017-02-08
- Published: 2017-09-07
- Earliest claimed: 2016-03-03
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Hongchun Yu; Weiran Lin; Shuguang Li; Guangming Yin
- Web page: https://patentgrep.com/patent/US20170257104A1

## CPC

- H03L 7/0814: {the phase shifting device being digitally controlled}
- H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence)
- H04L 7/0331: {with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence)}
- H03K 2005/00058: {controlled by a digital setting}
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Systems, methods, and apparatus are disclosed that that can improve robustness of digital phase locked loop (PLL) circuits. A method performed by a clock generation device includes generating a plurality of phase-shifted signals, each of the plurality of phase-shifted signals having a phase shift with respect to a base clock signal that is unique within the plurality of phase-shifted signals, selecting a first phase-shifted signal as an output signal, generating a first phase control word indicative of a second phase-shifted signal when the second signal has a closer phase relationship with a reference signal than the first signal, refraining from selecting the second signal as the output signal while either of the first signal and the second signal is in a first signaling state, and selecting as the output signal, the second signal when the first signal and the second signal are in a second signaling state.

## Claims

### Claim 1

A clock generation method, comprising:
generating a plurality of phase-shifted signals, each of the plurality of phase-shifted signals having a phase shift with respect to a base clock signal that is unique within the plurality of phase-shifted signals;
selecting as an output signal, a first signal in the plurality of phase-shifted signals;
generating a first phase control word indicative of a second signal in the plurality of phase-shifted signals when the second signal has a closer phase relationship with a reference signal than the first signal;
refraining from selecting the second signal as the output signal while either of the first signal and the second signal is in a first signaling state; and
selecting as the output signal, the second signal when the first signal and the second signal are in a second signaling state.

### Claim 2 (depends on 1)

The method of claim 1, wherein each pair of signals in the plurality of phase-shifted signals is separated by at least a minimum phase shift, and wherein the first signal is separated from the second signal by the minimum phase shift.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first signaling state corresponds to a logic low state when the second signal lags the first signal.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first signaling state corresponds to a logic high state when the second signal leads the first signal.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
generating a second phase control word configured to select a third signal in the plurality of phase-shifted signals; and
selecting the second signal as the output signal in accordance with timing of the third signal.

### Claim 6 (depends on 5)

The method of claim 5, wherein the timing of the third signal causes the second signal to be selected as the output signal when the first signal and the second signal are in the second signaling state.

### Claim 7 (depends on 5)

The method of claim 5, further comprising:
generating an indicator signal that indicates a phase relationship between the first signal and the second signal; and
using the indicator signal to generate the second phase control word.

### Claim 8 (depends on 5)

The method of claim 5, wherein the third signal is phase shifted with respect to the first signal and with respect to the second signal.

### Claim 9 (depends on 1)

The method of claim 1, further comprising:
generating a third phase control word configured to adjust phase of the base clock signal with respect to reference signal.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
adjusting timing of selection of the second signal as the output signal using the base clock signal,
wherein latency in the output signal is affected by adjusting the timing of selection of the second signal.

### Claim 11

An apparatus, comprising:
a first phase rotation circuit configured to select an output signal from a plurality of phase-shifted signals derived from a base clock signal, each of the plurality of phase-shifted signals having a phase shift with respect to a base clock signal that is unique within the plurality of phase-shifted signals;
a first control word generator adapted to produce phase control words that select an output signal from the plurality of phase-shifted signals as an output signal; and
a timing control circuit adapted to provide a first control word produced by the first control word generator to the first phase rotation circuit after a delay when the first control word is configured to change the output signal by selecting a first signal that has a closer phase relationship with a reference signal than the output signal,
wherein the delay prevents the timing control circuit from providing the first control word to the first phase rotation circuit while either of the first signal and the output signal is in a first signaling state.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein each pair of signals in the plurality of phase-shifted signals is separated by at least a minimum phase shift, and wherein the first signal is separated from the output signal by the minimum phase shift when the first control word is configured to change the output signal.

### Claim 13 (depends on 11)

The apparatus of claim 11, wherein the first signaling state corresponds to a logic low state when the output signal lags the first signal.

### Claim 14 (depends on 11)

The apparatus of claim 11, wherein the first signaling state corresponds to a logic high state when the output signal leads the first signal.

### Claim 15 (depends on 11)

The apparatus of claim 11, further comprising:
a second control word generator adapted to produce phase control words that select a sampling signal from the plurality of phase-shifted signals,
wherein the timing control circuit is configured to control the delay using the sampling signal.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the sampling signal determines when the first signal is selected as the output signal.

### Claim 17 (depends on 15)

The apparatus of claim 15, wherein the second control word generator is configured to generate an indicator signal that indicates a phase relationship between the first signal and the output signal, and wherein the indicator signal is used to generate the phase control words that select a sampling signal.

### Claim 18 (depends on 15)

The apparatus of claim 15, wherein the sampling signal is phase shifted with respect to the first signal and with respect to the output signal.

### Claim 19 (depends on 15)

The apparatus of claim 15, further comprising:
the phase control word is gated by the sampling signal until one or more resampled copies of the first phase control word match.

### Claim 20 (depends on 11)

The apparatus of claim 11, further comprising:
a second control word generator adapted to produce phase control words that adjust phase of the base clock signal with respect to reference signal.

### Claim 21

A clock generation apparatus, comprising:
means for generating a plurality of phase-shifted signals, each of the plurality of phase-shifted signals having a phase shift with respect to a base clock signal that is unique within the plurality of phase-shifted signals;
means for selecting an output signal from the plurality of phase-shifted signals, wherein a first signal in the plurality of phase-shifted signals is initially selected as the output signal; and
means for generating phase control words, wherein the means for generating phase control words is configured to generate a first phase control word that indicates a second signal in the plurality of phase-shifted signals when the second signal has a closer phase relationship with a reference signal than the first signal,
wherein the means for selecting the output signal from the plurality of phase-shifted signals is configured to:
refrain from selecting the second signal as the output signal while either of the first signal and the second signal is in a first signaling state; and
select the second signal as the output signal when the first signal and the second signal are in a second signaling state.

### Claim 22 (depends on 21)

The apparatus of claim 21, wherein each pair of signals in the plurality of phase-shifted signals is separated by at least a minimum phase shift, and wherein the first signal is separated from the second signal by the minimum phase shift.

### Claim 23 (depends on 21)

The apparatus of claim 21, wherein the first signaling state corresponds to a logic low state when the second signal lags the first signal.

### Claim 24 (depends on 21)

The apparatus of claim 21, wherein the first signaling state corresponds to a logic high state when the second signal leads the first signal.

### Claim 25 (depends on 21)

The apparatus of claim 21, wherein:
the means for generating phase control words is configured to generate a second phase control word that selects a third signal in the plurality of phase-shifted signals; and
wherein the means for selecting the output signal from the plurality of phase-shifted signals is configured to select the second signal as the output signal in accordance with timing of the third signal.

### Claim 26 (depends on 25)

The apparatus of claim 25, wherein the timing of the third signal causes the second signal to be selected as the output signal when the first signal and the second signal are in the second signaling state.

### Claim 27 (depends on 25)

The apparatus of claim 25, further comprising:
means for generating an indicator signal that indicates a phase relationship between the first signal and the second signal,
wherein the means for generating phase control words is configured to generate the second phase control word using the indicator signal.

### Claim 28 (depends on 25)

The apparatus of claim 25, wherein the third signal is phase shifted with respect to the first signal and with respect to the second signal.

### Claim 29 (depends on 21)

The apparatus of claim 21, further comprising:
means for generating a third phase control word configured to adjust phase of the base clock signal with respect to reference signal.

### Claim 30 (depends on 21)

The apparatus of claim 21, further comprising:
means for adjusting timing of selection of the second signal as the output signal using the base clock signal,
wherein the means for adjusting the timing of selection of the second signal is configured to modify latency in the output signal by adjusting the timing of selection of the second signal.