# US 2017/0257101 A1 · Configurable Gate Array Based on Three-Dimensional Writable Memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0257101 A1 - Document ID: US20170257101A1 - Status: Published application - Kind: A1 - Application number: 15/450,049 - Filed: 2017-03-06 - Published: 2017-09-07 - Earliest claimed: 2016-03-05 - Assignees: HangZhou HaiCun Information Technology Co., Ltd. - Inventors: Guobiao ZHANG - Web page: https://patentgrep.com/patent/US20170257101A1 ## CPC - H03K 19/1776: for memories - G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array - H03K 19/1737: {using multiplexers (H03K19/1738 takes precedence)} - H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables - H03K 19/17744: {for input/output signals} - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The present invention discloses a configurable gate array based on three-dimensional printed memory (3D-W). It comprises an array of configurable computing elements, an array of configurable logic elements and an array of configurable interconnects. Each configurable computing element comprises at least a 3D-W array, which is electrically programmable and can be loaded with a look-up table (LUT) for a math function. ## Claims ### Claim 1 A configurable gate array, comprising: at least a configurable logic element formed on a semiconductor substrate, wherein said configurable logic element selectively realizes a logic function from a logic library; and at least a first portion of a first configurable computing element formed in a first three-dimensional writable memory (3D-W) array stacked above said semiconductor substrate, wherein said first 3D-W array is electrically programmable and can be loaded with a first look-up table (LUT) for a first math function. ### Claim 2 (depends on 1) The configurable gate array according to claim 1, wherein said first 3D-W array at least partially covers said configurable logic element. ### Claim 3 (depends on 1) The configurable gate array according to claim 1, further comprising at least a configurable interconnect formed on said semiconductor substrate. ### Claim 4 (depends on 1) The configurable gate array according to claim 1, further comprising at least a multiplier formed on said semiconductor substrate. ### Claim 5 (depends on 1) The configurable gate array according to claim 1, further comprising at least a second portion of a second configurable computing element formed in a second 3D-W array stacked above said first 3D-W array, wherein said second 3D-W array is electrically programmable and can be loaded with a second LUT for a second math function; ### Claim 6 (depends on 1) The configurable gate array according to claim 1, wherein said first 3D-W array is electrically re-programmable and said first configurable computing element can be re-configured to realize different math functions. ### Claim 7 A configurable gate array, comprising: at least a configurable interconnect formed on a semiconductor substrate, wherein said configurable interconnect selectively realizes an interconnect from an interconnect library; and at least a first portion of a first configurable computing element formed in a first three-dimensional writable memory (3D-W) array stacked above said semiconductor substrate, wherein said first 3D-W array is electrically programmable and can be loaded with a first look-up table (LUT) for a first math function. ### Claim 8 (depends on 7) The configurable gate array according to claim 7, wherein said first 3D-W array at least partially covers said configurable interconnect. ### Claim 9 (depends on 7) The configurable gate array according to claim 7, further comprising at least a configurable logic element formed on said semiconductor substrate. ### Claim 10 (depends on 7) The configurable gate array according to claim 7, further comprising at least a multiplier formed on said semiconductor substrate. ### Claim 11 (depends on 7) The configurable gate array according to claim 7, further comprising at least a second portion of a second configurable computing element formed in a second 3D-W array stacked above said first 3D-W array, wherein said second 3D-W array is electrically programmable and can be loaded with a second LUT for a second math function; ### Claim 12 (depends on 7) The configurable gate array according to claim 7, wherein said first 3D-W array is electrically re-programmable and said first configurable computing element can be re-configured to realize different math functions. ### Claim 13 A configurable gate array, comprising: an array of configurable computing elements including a configurable computing element, wherein said configurable computing element is electrically programmable and can be loaded with a look-up table (LUT) for a math function; an array of configurable logic elements including a configurable logic element, wherein said configurable logic element selectively realizes a logic function from a logic library; an array of configurable interconnects including a configurable interconnect, wherein said array of configurable interconnects couple said array of configurable computing elements with said array of configurable logic elements; wherein said configurable gate array realizes a complex math function by programming said array of configurable computing elements, said array of configurable logic elements and said array of configurable interconnects. ### Claim 14 (depends on 13) The configurable gate array according to claim 13, wherein at least a portion of said configurable computing element is formed in a three-dimensional writable memory (3D-W) array stacked above a semiconductor substrate. ### Claim 15 (depends on 14) The configurable gate array according to claim 14, wherein said configurable logic element is formed on said semiconductor substrate. ### Claim 16 (depends on 15) The configurable gate array according to claim 15, wherein said 3D-W array at least partially covers said configurable logic element. ### Claim 17 (depends on 14) The configurable gate array according to claim 14, wherein said configurable interconnect is formed on said semiconductor substrate. ### Claim 18 (depends on 17) The configurable gate array according to claim 17, wherein said 3D-W array at least partially covers said configurable interconnect. ### Claim 19 (depends on 13) The configurable gate array according to claim 13, further comprising at least one multiplier. ### Claim 20 (depends on 14) The configurable gate array according to claim 14, wherein said 3D-W array is electrically re-programmable and said configurable computing element can be re-configured to realize different math functions.