# US 2017/0256709 A1 · Patterning methods, methods of fabricating semiconductor devices using the same, and semiconductor devices fabricated thereby

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2017/0256709 A1
- Document ID: US20170256709A1
- Status: Published application
- Kind: A1
- Application number: 15/598,605
- Filed: 2017-05-18
- Published: 2017-09-07
- Earliest claimed: 2015-01-23
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jongchul PARK; Hyungjoon KWON; lnho KIM; Jongsoon PARK
- Web page: https://patentgrep.com/patent/US20170256709A1

## CPC

- H10N 50/01: Manufacture or treatment
- H10P 50/262: {by physical means only}
- H10B 12/0387: {Making the trench}
- H10B 61/00: Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10N 50/10: Magnetoresistive devices
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A patterning method includes forming an etch-target layer on a substrate, forming mask patterns on the etch-target layer, and etching the etch-target layer using the mask patterns as an etch mask to form patterns spaced apart from each other. The etching process of the etch-target layer includes irradiating the etch-target layer with an ion beam, whose incident energy ranges from 600 eV to 10 keV. A recess region is formed in the etch-target layer between the mask patterns, and the ion beam is incident onto a bottom surface of the recess region at a first angle with respect to a top surface of the substrate and is incident onto an inner side surface of the recess region at a second angle with respect to the inner side surface of the recess region. The first angle ranges from 50° to 90° and the second angle ranges from 0° to 40°.

## Claims

### Claim 1

A semiconductor device, comprising:
an upper electrode on a substrate; and
a magnetic tunnel junction pattern between the substrate and the upper electrode,
wherein a maximum width of the upper electrode is larger than a maximum width of the magnetic tunnel junction pattern, and wherein the upper electrode has a width increasing in a direction away from a top surface of the substrate.

### Claim 2 (depends on 1)

The device of claim 1, wherein the magnetic tunnel junction pattern has a side surface that is perpendicular to the top surface of the substrate.

### Claim 3 (depends on 1)

The device of claim 1, wherein the magnetic tunnel junction pattern has a width that increases in a direction away from the top surface of the substrate.

### Claim 4 (depends on 1)

The device of claim 1, wherein the magnetic tunnel junction pattern comprises a first magnetic pattern and a second magnetic pattern, which are stacked on the substrate, and a tunnel barrier pattern interposed between the first and second magnetic patterns, and
wherein each of the first and second magnetic patterns has a magnetization direction that is perpendicular to an interface between the second magnetic pattern and the tunnel barrier pattern.

### Claim 5 (depends on 1)

The device of claim 1, wherein the magnetic tunnel junction pattern comprises a first magnetic pattern and a second magnetic pattern, which are stacked on the substrate, and a tunnel barrier pattern interposed between the first and second magnetic patterns, and
wherein each of the first and second magnetic patterns has a magnetization direction that is parallel to an interface between the second magnetic pattern and the tunnel barrier pattern.

### Claim 6 (depends on 1)

The device of claim 1, further comprising:
a lower electrode between the substrate and the magnetic tunnel junction pattern;
a selection element provided on the substrate and electrically connected to the magnetic tunnel junction pattern through the lower electrode; and
a bit line provided on the substrate and electrically connected to the magnetic tunnel junction pattern through the upper electrode.