# US 2017/0256643 A1 · Ultra High Voltage Device

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- Number: US 2017/0256643 A1
- Document ID: US20170256643A1
- Status: Published application
- Kind: A1
- Application number: 15/600,873
- Filed: 2017-05-22
- Published: 2017-09-07
- Earliest claimed: 2015-02-12
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: MING-FU TSAI; YU-TI SU; JEN-CHOU TSENG
- Web page: https://patentgrep.com/patent/US20170256643A1

## CPC

- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/605: {having significant overlap between the lightly-doped extensions and the gate electrode}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 30/655: {having edge termination structures}
- H10D 30/657: {having substrates comprising insulating layers, e.g. SOI-LDMOS transistors}
- H10D 30/6717: {the source and the drain regions being asymmetrical}
- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/125: {Shapes of junctions between the regions}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

According to an embodiment, a semiconductor device is provided. The device includes a second region having a greater curvature than a first region. The device includes an epitaxy layer of a first conductivity type, a well of a second conductivity type in the epitaxy layer, a drain in the epitaxy layer, a source in the well, and a bulk in the well and in contact with the source, the bulk having a greater area in the second region than in the first region.

## Claims

### Claim 1

A semiconductor device having a first region and a second region, the second region having a greater curvature than the first region, the device comprising:
an epitaxy layer of a first conductivity type in the first region and the second region;
a well of a second conductivity type in the epitaxy layer, the second conductivity type being different than the first conductivity type;
a first diffusion layer of the first conductivity type in the epitaxy layer;
a second diffusion layer of the first conductivity type in the well; and
a third diffusion layer of the second conductivity type in the well.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the third diffusion layer is separated from the second diffusion layer, a distance between the third diffusion layer and the second diffusion layer being smaller in the second region than in the first region.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, further comprising a shallow trench isolation (STI) region separating the third diffusion layer from the second diffusion layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the third diffusion layer is in contact with the second diffusion layer, the third diffusion layer (i) having a greater area in the second region than in the first region, and (ii) comprising a greater extension in the second region than in the first region.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein
the extension of the third diffusion layer has a plurality of discrete lateral extension portions toward the first diffusion layer, and
an area of each of the discrete lateral extension portions from the first region to the second region gradually increases.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, wherein the extension of the third diffusion layer is continuous and gradually increases from the first region to the second region.

### Claim 7

A semiconductor device having a first region and a second region, the second region having a greater curvature than the first region, the device comprising:
an epitaxy layer of a first conductivity type in the first region and the second region;
a well of a second conductivity type in the epitaxy layer, the second conductivity type being different than the first conductivity type;
a drain in the epitaxy layer;
a source in the well; and
a bulk in the well and separated from the source, wherein a distance between the bulk and the source is smaller in the second region than in the first region.

### Claim 8 (depends on 7)

The device of claim 7, wherein the drain comprises a first diffusion layer of the first conductivity type, the source comprises a second diffusion layer of the first conductivity type, and the bulk comprises a third diffusion layer of the second conductivity type.

### Claim 9 (depends on 7)

The device of claim 7, further comprising a shallow trench isolation (STI) region separating the bulk from the source.

### Claim 10 (depends on 9)

The device of claim 9, wherein the STI region is smaller in the second region than in the first region.

### Claim 11 (depends on 9)

The device of claim 9, wherein the STI region from the first region to the second region is continuous and gradually decreases.

### Claim 12 (depends on 7)

The device of claim 7, further comprising a well of the first conductivity type in the epitaxy layer, the drain being in the well of the first conductivity type.

### Claim 13 (depends on 7)

The device of claim 7, further comprising:
a polysilicon layer over a portion of the well of the second conductivity type; and
a gate oxide between the polysilicon layer and the well of the second conductivity type.

### Claim 14

A semiconductor device having a first region and a second region, the second region having a greater curvature than the first region, the device comprising:
an epitaxy layer of a first conductivity type in the first region and the second region;
a well of a second conductivity type in the epitaxy layer, the second conductivity type being different than the first conductivity type;
a first diffusion layer of the first conductivity type in the epitaxy layer;
a second diffusion layer of the first conductivity type in the well; and
a third diffusion layer of the second conductivity type in the well and in contact with the second diffusion layer, wherein the third diffusion layer comprises a greater extension in the second region than in the first region.

### Claim 15 (depends on 14)

The device of claim 14, wherein
the extension of the third diffusion layer has a plurality of discrete lateral extension portions toward the first diffusion layer, and
an area of each of the discrete lateral extension portions from the first region to the second region gradually increases.

### Claim 16 (depends on 14)

The device of claim 14, wherein the second diffusion has a smaller area in the second region than in the first region.

### Claim 17 (depends on 14)

The device of claim 14, wherein an area ratio of the third diffusion layer to the second diffusion layer in the second region is greater than that in the first region.

### Claim 18 (depends on 14)

The device of claim 14, further comprising a well of the first conductivity type in the epitaxy layer, the first diffusion layer being in the well of the first conductivity type.

### Claim 19 (depends on 14)

The device of claim 14, further comprising:
a polysilicon layer over a portion of the well of the second conductivity type; and
a gate oxide between the polysilicon layer and the well of the second conductivity type.

### Claim 20 (depends on 14)

The device of claim 14, wherein the extension of the third diffusion layer is continuous and gradually increases from the first region to the second region.