# US 2017/0256642 A1 · Tunneling Field Effect Transistor

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- Number: US 2017/0256642 A1
- Document ID: US20170256642A1
- Status: Published application
- Kind: A1
- Application number: 15/449,196
- Filed: 2017-03-03
- Published: 2017-09-07
- Earliest claimed: 2016-03-04
- Assignees: United Silicon Carbide, Inc.
- Applicants: United Silicon Carbide, Inc.
- Inventors: Xing Huang
- Web page: https://patentgrep.com/patent/US20170256642A1

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 12/021: {of gated diodes, e.g. field-controlled diodes [FCD]}
- H10D 12/211: {Gated diodes}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/635: {having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs}
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 62/142: {Anode regions of thyristors or collector regions of gated bipolar-mode devices}
- H10D 62/80: characterised by the materials
- H10D 62/8303: {Diamond}
- H10D 62/8325: {Silicon carbide}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A tunneling field-effect transistor with an insulated planar gate adjacent to a heterojunction between wide-bandgap semiconductor, such as silicon carbide, and either a narrow band gap material or a high work function metal. The heterojunction may be formed by filling a recess on a silicon carbide planar substrate, for example by etched into an epitaxially grown drift region atop the planar substrate. The low band gap material may be silicon which is deposited heterogeneously and, optionally, annealed via laser treatment and/or doped. The high work function metal may be tungsten, platinum, titanium, nickel, tantalum, or gold, or an alloy containing such a metal. The plane of the gate may be lateral or vertical. A blocking region of opposite doping type from the drift prevents conduction from the filled recess to the drift other than the conduction though the heterojunction.

## Claims

### Claim 1

A tunneling field-effect transistor, comprising:
a) a planar substrate, the planar substrate comprising a drain contact region below a drift region, where the drain contact region and the drift region comprise a wide-bandgap semiconductor of a first doping type;
b) a source region, where a first portion of the source region abuts the drift region at a junction, the source region comprising a narrow band gap semiconductor;
c) a blocking region, the blocking region being located between a second portion of the source region and the drift region, where the blocking region is of a second doping type, where the second doping type is different from the first doping type;
d) a source electrode, where the source electrode is connected to the source region and to the blocking region; and
e) a planar gate at an end of the junction, the gate comprising a gate electrode and a gate dielectric, where the plane of the gate is adjacent to the junction, a portion of the source region, and a portion of the drift region.

### Claim 2 (depends on 1)

The tunneling field-effect transistor of claim 1, wherein the wide-bandgap semiconductor has a bandgap greater than 2.0 eV.

### Claim 3 (depends on 1)

The tunneling field-effect transistor of claim 1, wherein the wide-bandgap semiconductor comprises silicon carbide, gallium nitride, diamond, or gallium oxide.

### Claim 4 (depends on 2)

The tunneling field-effect transistor of claim 2, wherein the bandgap of the wide-bandgap semiconductor is greater than a bandgap of the narrow bandgap semiconductor by at least 0.4 electron volts.

### Claim 5 (depends on 1)

The tunneling field-effect transistor of claim 1, wherein the source region comprises silicon.

### Claim 6 (depends on 2)

The tunneling field-effect transistor of claim 2, wherein the source region comprises crystalline silicon.

### Claim 7 (depends on 1)

The tunneling field-effect transistor of claim 1, wherein the plane of the gate is substantially parallel to the plane of the planar substrate.

### Claim 8 (depends on 1)

The tunneling field-effect transistor of claim 1, wherein the plane of the gate is substantially perpendicular to the plane of the planar substrate.

### Claim 9

A tunneling field-effect transistor, comprising:
a) a planar substrate, the planar substrate comprising a drain contact region below a drift region, where the drain contact region and the drift region comprise a wide-bandgap semiconductor are of a first doping type;
b) a source region, where a first portion of the source region abuts the drift region at a junction, the source region comprising a high work function metal;
c) a blocking region, the blocking region being located between a second portion of the source region and the drift region, where the blocking region is of a second doping type, where the second doping type is different from the first doping type;
d) a source electrode, where the source electrode is connected to the source region and to the blocking region; and
e) a planar gate at an end of the junction, the gate comprising a gate electrode and a gate dielectric, where the plane of the gate is adjacent to the junction, a portion of the source region, and a portion of the drift region.

### Claim 10 (depends on 9)

The tunneling field-effect transistor of claim 9, wherein the high work function metal has a work function of 3.0 eV or higher.

### Claim 11 (depends on 9)

The tunneling field-effect transistor of claim 9, wherein the source region comprises tungsten, nickel, gold, or titanium.

### Claim 12 (depends on 9)

The tunneling field-effect transistor of claim 9, wherein the plane of the gate is substantially parallel to the plane of the planar substrate.

### Claim 13 (depends on 9)

The tunneling field-effect transistor of claim 9, wherein the plane of the gate is substantially perpendicular to the plane of the planar substrate.

### Claim 14 (depends on 9)

The tunneling field-effect transistor of claim 9, wherein the wide-bandgap semiconductor has a bandgap greater than 2.0 eV.

### Claim 15 (depends on 9)

The tunneling field-effect transistor of claim 9, wherein the wide-bandgap semiconductor comprises silicon carbide, gallium nitride, diamond, or gallium oxide.

### Claim 16

A method of manufacturing a tunneling field-effect transistor, comprising:
a) etching a notch into an upper drift region of a planar substrate, the planar substrate comprising a drain contact region below a drift region, where the drain contact region and the drift region comprise a wide-bandgap semiconductor, the wide bandgap semiconductor having a bandgap greater than 2.0 electron volts, where the wide-bandgap semiconductor comprises silicon carbide, gallium nitride, diamond, or gallium oxide;
b) forming a blocking region beneath the notch by implantation of an exposed portion of the drift region, where the blocking region is a of second doping type, where the second doping type is different from the first doping type;
c) filling the notch with a non-wide band gap material to form a source region, where a first portion of the source region abuts the drift region at a junction;
d) placing a planar gate at an exposed end of the junction, the gate comprising a gate electrode and a gate dielectric, where the plane of the gate extends over the end of the junction, over a portion of the source region, and over a portion of the drift region; and
e) connecting a source electrode to the source region.

### Claim 17 (depends on 16)

The method of claim 16, wherein the non-wide band gap material is a high work function metal.

### Claim 18 (depends on 16)

The method of claim 16, wherein the non-wide band gap material is silicon.

### Claim 19 (depends on 18)

The method of claim 18, further comprising:
a) depositing the silicon in heterogeneous form;
b) crystallizing the silicon via laser stimulation.

### Claim 20 (depends on 16)

The method of claim 16, further comprising:
a) exposing the end of junction by etching a trench adjacent to the source region, where the trench abuts the source region and the blocking region;
b) forming a dielectric on a wall of the trench;
c) placing the gate electrode adjacent to the dielectric on the wall of the trench.