# US 2017/0256641 A1 · Semiconductor Device Comprising a First Gate Electrode and a Second Gate Electrode

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- Number: US 2017/0256641 A1
- Document ID: US20170256641A1
- Status: Published application
- Kind: A1
- Application number: 15/060,790
- Filed: 2016-03-04
- Published: 2017-09-07
- Earliest claimed: 2016-03-04
- Assignees: Infineon Technologies AG
- Applicants: Infineon Technologies AG
- Inventors: Andreas Meiser
- Web page: https://patentgrep.com/patent/US20170256641A1

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)}
- H10D 30/658: {having trench gate electrodes}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/112: {comprising multiple field plate segments}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a transistor. The transistor includes a source region and a drain region disposed adjacent to a first main surface of a semiconductor substrate, a first gate electrode and a second gate electrode, the first gate electrode being disconnected from the second gate electrode. The transistor further includes a body region. The first gate electrode is adjacent to a first portion of the body region and the second gate electrode is adjacent to a second portion of the body region. The transistor further includes first trenches patterning the first portion of the body region into a first ridge, and second trenches patterning the second portion of the body region into a second ridge. The first gate electrode is arranged in at least one of first trenches, and the second gate electrode is arranged in at least one of the second trenches.

## Claims

### Claim 1

A semiconductor device comprising a transistor, the transistor comprising:
a source region and a drain region disposed adjacent to a first main surface of a semiconductor substrate;
a first gate electrode and a second gate electrode, the first gate electrode being disconnected from the second gate electrode;
a body region, the first gate electrode being adjacent to a first portion of the body region and the second gate electrode being adjacent to a second portion of the body region;
first trenches patterning the first portion of the body region into a first ridge; and
second trenches the second portion of the body region into a second ridge,
wherein the first gate electrode is arranged in at least one of the first trenches,
wherein the second gate electrode is arranged in at least one of the second trenches.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first trenches and the second trenches have a longitudinal axis parallel to the first main surface and extending along a line connecting the source region and the drain region.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising a connection portion configured to electrically connect the first portion of the body region with the second portion of the body region.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the connection portion comprises a doped substrate portion disposed in a connection groove.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the connection groove extends to a depth of the first or second trenches.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising a drift zone between the second portion of the body region and the drain region.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising a source contact extending to a second main surface of the semiconductor substrate.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising a drain contact extending to a second main surface of the semiconductor substrate.

### Claim 9 (depends on 6)

The semiconductor device of claim 6, further comprising a field plate adjacent to the drift zone.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the field plate is disposed in field plate trenches that pattern the drift zone into a third ridge.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the field plate trenches extend to a deeper depth than the first and second trenches.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein the field plate is disposed in at least one of the second trenches.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein the field plate and the second gate electrode are electrically coupled to a second gate terminal.

### Claim 14 (depends on 5)

The semiconductor device of claim 5, wherein the first gate trenches extend along a first gate length and the second gate trenches extend along a second gate length, the second gate length being larger than the first gate length.

### Claim 15 (depends on 1)

The semiconductor device of claim 1, further comprising a vertical body contact portion electrically connected to a source contact and to the body region, the vertical body contact portion vertically overlapping with the source region.

### Claim 16 (depends on 1)

The semiconductor device of claim 1, further comprising a source contact in a source contact groove in the first main surface, wherein the source region and a vertical body contact portion are alternatingly disposed at a sidewall of the source contact groove.

### Claim 17 (depends on 1)

The semiconductor device of claim 1, further comprising a drain contact in a drain contact groove in the first main surface, wherein the drain groove is formed in the body region.