# US 2017/0256629 A1 · Method for manufacturing semiconductor element and method for forming mask pattern of the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0256629 A1 - Document ID: US20170256629A1 - Status: Published application - Kind: A1 - Application number: 15/263,800 - Filed: 2016-09-13 - Published: 2017-09-07 - Earliest claimed: 2016-03-03 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Kabushiki Kaisha Toshiba - Inventors: Masafumi HAMAGUCHI - Web page: https://patentgrep.com/patent/US20170256629A1 ## CPC - H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations} - H10D 30/0223: {having source and drain regions or source and drain extensions self-aligned to sides of the gate} - H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)} - H10P 30/204: {into Group IV semiconductors} - H10P 30/21: {of electrically active species} - H10P 30/22: using masks - H10P 30/221: {characterised by the angle between the ion beam and the mask} - H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)} - H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations - H10W 20/0698: {Local interconnections} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A method for manufacturing a semiconductor element includes forming a first region in a semiconductor region by ion-implanting impurities using a first mask; forming an interconnect including a gate portion extending in a first direction over the first region; and forming a source/drain region by ion-implanting impurities into a second region. A gate threshold voltage of the semiconductor element has first to third correlations dependent respectively on distances between an inner wall of the first mask and an outer edge of the second region, between the gate portion and the outer edge of the second region and between the outer edge of the second portion and a portion of the interconnect other than the gate portion. At least one of the distances is determined based on the first to third correlations to obtain a prescribed gate threshold voltage of the semiconductor element. ## Claims ### Claim 1 A method for manufacturing a semiconductor element, the method comprising: forming a first region of a first conductivity type in a semiconductor region by selectively ion-implanting impurities of the first conductivity type using a first mask provided on the semiconductor region, the first mask having a first opening, the first region being exposed at a bottom surface of the first opening; forming an interconnect including a gate portion extending in a first direction over the first region; and forming a source and a drain by ion-implanting impurities of a second conductivity type into a second region, the second region being positioned on two sides of the gate portion in the first region, a gate threshold voltage of the semiconductor element having: a first correlation dependent on a first distance to an inner wall of the first opening from an outer edge of the second region proximal to the inner wall of the first opening, a second correlation dependent on a second distance from the outer edge of the second region to the gate portion in a second direction intersecting the first direction, a third correlation dependent on a third distance in one of the first direction and the second direction to the outer edge of the second region from a portion of the interconnect positioned outside the second region, and a fourth correlation dependent on a fourth distance when impurities of the first conductivity type are selectively ion-implanted under the gate portion using a second mask provided on the semiconductor region, the fourth distance being the distance to an inner wall of a second opening of the second mask from the outer edge of the second region proximal to the inner wall of the second opening, and at least one of the first distance, the second distance, the third distance, and the fourth distance being determined based on the first correlation, the second correlation, the third correlation and the fourth correlation to obtain a prescribed gate threshold voltage of the semiconductor element. ### Claim 2 (depends on 1) The method according to claim 1, wherein the first distance is the shortest distance to the inner wall of the first opening from the outer edge of the second region; and the fourth distance is the shortest distance to the outer edge of the second region from the inner wall of a second opening of the second mask. ### Claim 3 (depends on 1) The method according to claim 1, wherein the absolute value of the gate threshold voltage increases in the first correlation as the first distance shortens. ### Claim 4 (depends on 1) The method according to claim 1, wherein the second region is formed to include a first portion positioned on one side of the gate portion in the second direction and a second portion positioned on the other side of the gate portion in the second direction. ### Claim 5 (depends on 4) The method according to claim 4, wherein the first portion of the second region has a first width in the second direction, the second portion of the second region has a second width in the second direction, and at least one of the first width or the second width is determined as the second distance. ### Claim 6 (depends on 5) The method according to claim 5, wherein the second region is formed to have the second width different from the first width. ### Claim 7 (depends on 1) The method according to claim 1, further comprising: forming an insulating layer surrounding the second region. ### Claim 8 (depends on 1) The method according to claim 1, wherein the interconnect includes a first portion, a second portion, and a connection portion, the first portion extending in the first direction and including the gate portion, the second portion extending in the second direction outside the second region, the connection portion linking the first portion to the second portion, the connection portion having an outer edge having a curvature, and the third distance is a distance between the second portion and the second region at a position separated from the outer edge of the connection portion. ### Claim 9 (depends on 4) The method according to claim 4, wherein the second region further has a third portion and a connection portion, the third portion extending in the first direction and being linked to the first portion or the second portion, the connection portion linking the third portion to the first portion or the second portion, the connection portion having an outer edge having a curvature, and the third distance is a distance in the second direction to the interconnect from the third portion at a position separated from the outer edge of the connection portion. ### Claim 10 (depends on 1) The method according to claim 1, wherein the absolute value of the gate threshold voltage increases in the third correlation as the third distance shortens. ### Claim 11 (depends on 1) The method according to claim 1, wherein the absolute value of the gate threshold voltage increases in the fourth correlation as the fourth distance shortens. ### Claim 12 (depends on 1) The method according to claim 1, wherein the fourth correlation includes a dependency of the gate threshold voltage on a thickness of the second mask in a third direction, the third direction being perpendicular to a front surface of the semiconductor region. ### Claim 13 A method for forming a mask pattern of a semiconductor element, the method comprising: forming a mask pattern group based on a prescribed rule of providing the semiconductor element with a first gate threshold voltage, the mask pattern group including: a well pattern defining a first region on a semiconductor region; an interconnect pattern defining an interconnect including a gate portion extending in a first direction on the first region; and a source/drain pattern defining a second region positioned in the first region, the gate portion crossing the second region in the first direction. modifying at least one of a first distance, a second distance, a third distance and a fourth distance based on a first correlation, a second correlation, a third correlation and a fourth correlation of a gate threshold voltage of the semiconductor element to obtain a second gate threshold voltage, wherein the gate threshold voltage in the first correlation depends on the first distance to an outer edge of the first region from an outer edge of the second region proximal to the outer edge of the first region; the gate threshold voltage in the second correlation depends on the second distance from the outer edge of the second region to the gate portion in a second direction intersecting the first direction; the gate threshold voltage in the third correlation depends on the third distance to the second region from a portion of the interconnect positioned outside the second region in one of the first direction or the second direction; and the gate threshold voltage in the fourth correlation depends on the fourth distance when the mask pattern group further includes an ion implantation pattern defining an opening exposing the gate portion, the fourth distance being the distance to a wall surface of the opening from the outer edge of the second region proximal to the wall surface of the opening. ### Claim 14 (depends on 13) The method according to claim 13, wherein the second correlation includes a dependency of the gate threshold voltage on a distance to the gate portion from one outer edge of the second region in the second direction and on a distance to the gate portion from the other outer edge of the second region in the second direction. ### Claim 15 (depends on 13) The method according to claim 13, wherein the interconnect includes a first portion and a second portion, the first portion extending in the first direction and including the gate portion, the second portion extending in the second direction, and the third distance is a distance from the second portion to the second region. ### Claim 16 (depends on 13) The method according to claim 13, wherein the second region includes a first portion and a second portion, the first portion crossing the gate portion, the second portion extending in the first direction, and the third distance is a distance to the second portion of the second region from a portion of the interconnect extending in the first direction.