# US 2017/0256609 A1 · Semiconductor device

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- Number: US 2017/0256609 A1
- Document ID: US20170256609A1
- Status: Published application
- Kind: A1
- Application number: 15/296,077
- Filed: 2016-10-18
- Published: 2017-09-07
- Earliest claimed: 2016-03-02
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Krishna Kumar BHUWALKA; Seong-Je KIM; Jong-Chol KIM; Hyun-Woo KIM
- Web page: https://patentgrep.com/patent/US20170256609A1

## CPC

- H10D 62/118: {Nanostructure semiconductor bodies}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/0193: {by modifying properties of the stacked channels}
- H10D 30/0194: {the stacked channels having different properties}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/506: {having different thicknesses, sizes or shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device includes a plurality of channels, source/drain layers, and a gate structure. The channels are sequentially stacked on a substrate and are spaced apart from each other in a first direction perpendicular to a top surface of the substrate. The source/drain layers are connected to the channels and are at opposite sides of the channels in a second direction parallel to the top surface of the substrate. The gate structure encloses the channels. The channels have different lengths in the second direction and different thicknesses in the first direction.

## Claims

### Claim 1

A semiconductor device, comprising:
a plurality of channels sequentially stacked on a substrate, the plurality of channels spaced apart from each other in a first direction perpendicular to a top surface of the substrate;
source/drain layers at opposite sides of the plurality of channels in a second direction parallel to the top surface of the substrate, the source/drain layers connected to the plurality of channels; and
a gate structure enclosing the plurality of channels, wherein the plurality of channels have different lengths in the second direction and different thicknesses in the first direction.

### Claim 2 (depends on 1)

The semiconductor device as claimed in claim 1, wherein the thicknesses of the plurality of channels in the first direction are in a proportional relationship to the lengths of the plurality of channels in the second direction.

### Claim 3 (depends on 2)

The semiconductor device as claimed in claim 2, wherein:
the lengths of the plurality of channels in the second direction increase in a predetermined direction, and
the thicknesses of the plurality of channels in the first direction increase in the predetermined direction.

### Claim 4 (depends on 2)

The semiconductor device as claimed in claim 2, wherein:
a length of each of an uppermost channel and a lowermost channel of the plurality of channels in the second direction is greater than a length of an intermediate channel of the plurality of channels in the second direction, and
a thickness of each of the uppermost channel and the lowermost channel of the plurality of channels in the first direction is greater than a thickness of the intermediate channel of the plurality of channels in the first direction.

### Claim 5 (depends on 1)

The semiconductor device as claimed in claim 1, wherein each of the source/drain layers includes:
an epitaxial layer on the substrate; and
extension portions extending from the epitaxial layer in the second direction and respectively connected to the plurality of channels.

### Claim 6 (depends on 5)

The semiconductor device as claimed in claim 5, wherein the extension portions include:
substantially a same material as the plurality of channels, and
a same impurity as the epitaxial layer.

### Claim 7 (depends on 5)

The semiconductor device as claimed in claim 5, wherein the epitaxial layer and the extension portions include different materials and a same impurity.

### Claim 8 (depends on 5)

The semiconductor device as claimed in claim 5, wherein:
the epitaxial layer has a substantially vertical sidewall along the first direction, and
the extension portions have lengths in the second direction that progressively decrease in a downward direction.

### Claim 9 (depends on 5)

The semiconductor device as claimed in claim 5, wherein:
the epitaxial layer has a width in the second direction that progressively decreases in a predetermined direction, and
the extension portions have a constant length in the second direction in the predetermined direction.

### Claim 10 (depends on 5)

The semiconductor device as claimed in claim 5, wherein:
the epitaxial layer has a greater width in the second direction at a middle portion than at an upper portion or at a lower portion, and
extension portions have a substantially constant length in the second direction.

### Claim 11 (depends on 5)

The semiconductor device as claimed in claim 5, further comprising:
an inner spacer between the gate structure and the epitaxial layer.

### Claim 12 (depends on 11)

The semiconductor device as claimed in claim 11, wherein the gate structure includes:
a gate insulating pattern enclosing each of the plurality of channels; and
a gate electrode at least partially covered by the gate insulating patterns, the gate electrode extending in a third direction parallel to the top surface of the substrate and perpendicular to the second direction.

### Claim 13

A semiconductor device, comprising:
a pair of first semiconductor patterns on a substrate, the pair of first semiconductor patterns spaced apart from each other in a first direction parallel to a top surface of the substrate;
second semiconductor patterns between the pair of first semiconductor patterns and connected to the pair of first semiconductor patterns, the second semiconductor patterns spaced apart from each other in a second direction perpendicular to the top surface of the substrate; and
a gate structure between the pair of first semiconductor patterns and covering the second semiconductor patterns, wherein each of the second semiconductor patterns includes a central portion between end portions in the first direction, the end portions of the second semiconductor patterns including a same impurity as the pair of first semiconductor patterns, and the central portions of the second semiconductor patterns having different lengths and different thicknesses from each other.

### Claim 14 (depends on 13)

The semiconductor device as claimed in claim 13, wherein the thicknesses of the central portions of the second semiconductor patterns are in a proportional relationship to the lengths of the central portions of the semiconductor patterns.

### Claim 15 (depends on 14)

The semiconductor device as claimed in claim 14, wherein the thicknesses and the lengths of the central portions of the second semiconductor patterns increase in a predetermined direction.

### Claim 16

(canceled)

### Claim 17 (depends on 13)

The semiconductor device as claimed in claim 13, wherein:
the pair of first semiconductor patterns have substantially vertical sidewalls in the second direction, and
the lengths of the end portions of the second semiconductor patterns decrease in a predetermined direction.

### Claim 18 (depends on 13)

The semiconductor device as claimed in claim 13, wherein:
the pair of first semiconductor patterns have a width decreasing in a predetermined direction, and
the lengths of the end portions of the second semiconductor patterns are substantially constant in the predetermined direction.

### Claim 19 (depends on 18)

The semiconductor device as claimed in claim 18, wherein the gate structure includes a gate insulating pattern partially enclosing the second semiconductor patterns, and a gate electrode at least partially covered by the gate insulating patterns.

### Claim at position 20

20-23. (canceled)

### Claim 24

A semiconductor device, comprising:
a plurality of patterns stacked on a substrate; and
a plurality of gate electrodes on respective ones of the patterns,
wherein the patterns include channels and wherein lengths of the channels or gate electrodes progressively change to offset a progressive change in thicknesses of the channels or gate electrodes in a predetermined direction.

### Claim 25 (depends on 24)

The semiconductor device as claimed in claim 24, further comprising:
a plurality of source/drain layers adjacent respective sides of the patterns,
wherein at least one of the channels or the source/drain layers have a non-uniform doping profile.

### Claim at position 23

26-27. (canceled)