# US 2017/0256608 A1 · Semiconductor device and method for fabricating the same

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- Number: US 2017/0256608 A1
- Document ID: US20170256608A1
- Status: Published application
- Kind: A1
- Application number: 15/444,550
- Filed: 2017-02-28
- Published: 2017-09-07
- Earliest claimed: 2016-03-02
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sung Dae SUK; Seung Min SONG; Geum Jong BAE
- Web page: https://patentgrep.com/patent/US20170256608A1

## CPC

- H10D 30/0195: {forming inner spacers between adjacent channels, e.g. changing their shapes or sizes}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/507: {characterised by inner spacers between adjacent channels}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D 64/675: {Gate sidewall spacers}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 62/121: {oriented parallel to substrates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device may include a substrate, a first nanowire, a gate electrode, a first gate spacer, a second gate spacer, a source/drain and a spacer connector. The first nanowire may be extended in a first direction and spaced apart from the substrate. The gate electrode may surround a periphery of the first nanowire, and extend in a second direction intersecting the first direction, and include first and second sidewalls opposite to each other. The first gate spacer may be formed on the first sidewall of the gate electrode. The first nanowire may pass through the first gate spacer. The second gate spacer may be formed on the second sidewall of the gate electrode. The first nanowire may pass through the second gate spacer. The source/drain may be disposed on at least one side of the gate electrode and connected with the first nanowire. The spacer connector may be disposed between the first nanowire and the substrate. The spacer connector may connect the first gate spacer and the second gate spacer to each other.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a first nanowire extended in a first direction and spaced apart from the substrate;
a gate electrode surrounding a periphery of the first nanowire, extending in a second direction intersecting the first direction, and comprising first and second sidewalls opposite to each other;
a first gate spacer formed on the first sidewall of the gate electrode, wherein the first nanowire passes through the first gate spacer;
a second gate spacer formed on the second sidewall of the gate electrode, wherein the first nanowire passes through the second gate spacer;
a source/drain disposed on at least one side of the gate electrode and connected with the first nanowire; and
a spacer connector disposed between the first nanowire and the substrate, wherein the spacer connector connects the first gate spacer and the second gate spacer to each other.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first gate spacer comprises a first outer spacer contacting top and side surfaces of the first nanowire, and a first inner spacer contacting a lower surface of the first nanowire,
wherein the second gate spacer comprises a second outer spacer contacting the top and side surfaces of the first nanowire and a second inner spacer contacting the lower surface of the first nanowire,
wherein the first outer spacer and the first inner spacer comprise different materials from each other, and
wherein the second outer spacer and the second inner spacer comprise different materials from each other.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the first and second inner spacers comprise the same material as each other.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein the first and second outer spacers are spaced apart from each other,
wherein the first and second inner spacers are connected to each other through the spacer connector.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the spacer connector and the first and second inner spacers are a single integrated structure.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising a second nanowire disposed on the first nanowire and extended in the first direction, wherein the first nanowire and the second nanowire are spaced apart from each other.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the first gate spacer comprises a first outer spacer contacting top and side surfaces of the second nanowire and a side surface of the first nanowire, a first upper inner spacer contacting a lower surface of the second nanowire and a top surface of the first nanowire, and a first lower inner spacer contacting a lower surface of the first nanowire, and
wherein the second gate spacer comprises a second outer spacer contacting the top and side surfaces of the second nanowire and the side surface of the first nanowire, a second upper inner spacer contacting the lower surface of the second nanowire and the top surface of the first nanowire, and a second lower inner spacer contacting the lower surface of the first nanowire.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the first upper inner spacer and the first lower inner spacer comprise the same material as each other, and
wherein the second upper inner spacer and the second lower inner spacer comprise the same material as each other.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, wherein the first lower inner spacer and the second lower inner spacer are connected to each other through the spacer connector.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the spacer connector comprises an insulating material.

### Claim 11

A semiconductor device, comprising:
a substrate;
a first nanowire extended in a first direction and spaced apart from the substrate;
a gate electrode surrounding a periphery of the first nanowire and extending in a second direction intersecting the first direction;
a gate spacer disposed on a sidewall of the gate electrode, wherein the gate spacer comprises inner and outer sidewalls opposite to each other, and the inner sidewall of the gate spacer faces the gate electrode;
a source/drain disposed on at least one side of the gate electrode and connected with the first nanowire, wherein the first nanowire passes through the gate spacer to be connected to the source/drain; and
an inner spacer comprising a protruding portion disposed between the substrate and the first nanowire and contacting a lower surface of the first nanowire, and a spaced portion connected to the protruding portion and spaced apart from the lower surface of the first nanowire.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the gate electrode comprises first and second side surfaces opposite to each other, and
wherein the protruding portion comprises a first protruding portion which is in contact with the first side surface of the gate electrode, and a second protruding portion which is in contact with the second side surface of the gate electrode.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the gate spacer comprises a first gate spacer which is in contact with the first side surface and a second gate spacer which is in contact with the second side surface,
wherein a thickness of the first protruding portion is the same as that of the first gate spacer and a thickness of the second protruding portion is the same as that of the second gate spacer.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, wherein a length of the inner spacer in the first direction is the same as that of the first nanowire in the first direction.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, wherein the gate electrode is disposed between the spaced portion and the first nanowire.

### Claim 16

A semiconductor device, comprising:
a substrate;
a first nanowire extended in a first direction and spaced apart from the substrate;
a gate electrode surrounding a periphery of the first nanowire and extending in a second direction intersecting the first direction;
a gate spacer disposed on a sidewall of the gate electrode, wherein the gate spacer comprises inner and outer sidewalls opposite to each other, and the inner sidewall of the gate spacer faces the gate electrode;
a source/drain disposed on at least one side of the gate electrode and connected with the first nanowire, wherein the first nanowire passes through the gate spacer to be connected to the source/drain; and
an inner spacer disposed between the substrate and the first nanowire,
wherein a material included in the gate spacer has a first dielectric constant and a material included in the inner spacer has a second dielectric constant different from the first dielectric constant.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the second dielectric constant is lower than the first dielectric constant.

### Claim 18 (depends on 16)

The semiconductor device of claim 16, further comprising a second nanowire disposed on the first nanowire and extended in the first direction, wherein the first nanowire and the second nanowire are spaced apart from each other in a manner such that a height from an uppermost surface of the substrate to a lowermost surface of the second nanowire is greater than a height from the uppermost surface of the substrate to a lowermost surface of the first nanowire.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, further comprising a third nanowire disposed on the second nanowire and extended in the first direction, wherein the second nanowire and the third nanowire are spaced apart from each other in a manner such that a height from the uppermost surface of the substrate to a lowermost surface of the third nanowire is greater than a height from the uppermost surface of the substrate to the lowermost surface of the second nanowire.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, wherein a length of the inner spacer in the first direction is the same as that of the first nanowire in the first direction.