# US 2017/0256607 A1 · Power semiconductor device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2017/0256607 A1
- Document ID: US20170256607A1
- Status: Published application
- Kind: A1
- Application number: 15/598,730
- Filed: 2017-05-18
- Published: 2017-09-07
- Earliest claimed: 2015-05-12
- Assignees: MagnaChip Semiconductor, Ltd.
- Applicants: Magnachip Semiconductor, Ltd.
- Inventors: In Su KIM; Jeong Hwan PARK; Seung Sik PARK; Ha Yong YANG
- Web page: https://patentgrep.com/patent/US20170256607A1

## CPC

- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 64/111: {Field plates}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10W 20/43: Layouts of interconnections
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present examples relate to a power semiconductor device. The present examples also relate to a power semiconductor device that maintains a breakdown voltage and reduces a gate capacitance through improving the structure of an Injection Enhanced Gate Transistor (IEGT), and thereby reduces strength of an electric field compared to alternative technologies. Accordingly, the present examples provide a power semiconductor device with a small energy consumption and with an improved switching functionality.

## Claims

### Claim 1

A power semiconductor device comprising:
a substrate having a first surface and a second surface opposite to the first surface;
a drift region having a first conductivity type;
an emitter electrode located on the first surface of the substrate;
a drain electrode located on the second surface of the substrate;
an emitter contact region in contact with the emitter electrode;
a base region of a second conductivity type between the emitter contact region and the drift region;
an electrically floating region having an impurity concentration lower than an impurity concentration of the base region; and
a trench structure comprising a plurality of walls enclosing a region of the substrate,
wherein the walls extend from the first surface of the substrate toward the drift region and separate the emitter contact region from the electrically floating region, and
wherein the electrically floating region covers an end surface of each of the walls of the trench gate structure and prevents contact of the end surfaces with the drift region.

### Claim 2 (depends on 1)

The power semiconductor device of claim 1, wherein the trench structure comprises a trench gate structure, the emitter contact region is within the enclosed area and the electrically floating region surrounds the trench structure.

### Claim 3 (depends on 1)

The power semiconductor device of claim 1, wherein the trench structure comprises a trench emitter structure, the electrically floating region is within the enclosed area, and the emitter contact region surrounds the trench structure.

### Claim 4 (depends on 2)

The power semiconductor device of claim 2, further comprising:
a first well region with the first conductivity type disposed between the base region and the drift region and having a higher impurity concentration than the drift region,
wherein the emitter contact region comprises a first conductivity type source region and a second conductivity type contact region, and
wherein the floating region and the base region are separated by the first well region.

### Claim 5 (depends on 2)

The power semiconductor device of claim 2, further comprising:
a second conductivity type deep-well region having a greater depth than the floating region,
wherein the floating region is bounded by a first trench structure, the deep-well region is bounded by a second trench structure, and the first and second trench structures are separated by the drift region.

### Claim 6 (depends on 1)

The power semiconductor device of claim 1, wherein the substrate further comprises a termination region surrounding a cell region, the cell region comprises the emitter contact region and the floating region, and the termination region comprises a termination ring region and a gate bus line.

### Claim 7 (depends on 1)

The power semiconductor device of claim 1, further comprising:
a termination ring region located in the substrate;
a first trench structure bounding the floating region; and
a second conductivity type deep-well region located between the first trench structure and the termination ring region and having a deeper depth than the floating region,
wherein the deep-well region is electrically connected to the emitter electrode.

### Claim 8 (depends on 7)

The power semiconductor device of claim 7, further comprising:
a second conductivity type edge base region located between the first trench structure and the deep-well region, and having a smaller depth than the first trench structure.

### Claim 9

A power semiconductor substrate comprising:
a substrate comprising a first conductivity type drift region;
an emitter electrode located on an upper region of the substrate;
a drain electrode located on a lower region of the substrate;
an emitter contact region in contact with the emitter electrode;
a second conductivity type base region formed below the emitter contact region;
a second conductivity type floating region located in the trench emitter structure with a greater depth than the depth of the trench emitter structure;
a first trench structure comprising a plurality of walls enclosing a region of the substrate, extending from the upper region of the substrate toward the drift region, and separating the emitter contact region from the floating region; and
a second trench structure surrounding the first trench structure;
wherein the second conductivity type floating region is electrically floating.

### Claim 10 (depends on 9)

The power semiconductor substrate of claim 9, wherein
the first trench structure comprises a trench emitter structure,
the second trench structure comprises a trench gate structure,
the floating region is in the region enclosed by the trench emitter structure, and
the emitter contact region is between the trench emitter structure and the trench gate structure.

### Claim 11 (depends on 10)

The power semiconductor substrate of claim 10, wherein the floating region covers an end surface of each of the walls of the trench emitter structure, preventing contact of the end surfaces with the drift region.

### Claim 12 (depends on 10)

The power semiconductor substrate of claim 10, wherein the trench gate structure surrounding the trench emitter structure is a portion of a network structure having at least one other portion comprising another trench gate structure surrounding another trench emitter structure.

### Claim 13 (depends on 10)

The power semiconductor substrate of claim 10, wherein
the trench gate structure surrounding the trench emitter structure is a first trench region of a trench gate network,
the trench gate network comprises other trench regions each surrounding a trench emitter structure and an emitter contact region, and
the emitter contact region in each trench region comprises a first conductivity type source region and a second conductivity type contact region.

### Claim 14 (depends on 12)

The power semiconductor substrate of claim 12, wherein the source region is formed only on a side of the emitter contact region adjacent to the trench gate structure.

### Claim 15 (depends on 9)

The power semiconductor substrate of claim 9, further comprising:
a second conductivity type termination ring region formed in a perimeter of the substrate; and
a dummy trench gate formed between the termination ring region and the second trench structure.

### Claim 16 (depends on 9)

The power semiconductor substrate of claim 9, wherein
the substrate is divided into regions each comprising a first trench structure and a second trench structure,
first type regions and second type regions are formed alternately on the substrate,
in each first type region, the first trench structure is a trench gate structure and a floating region surrounds the trench gate structure, and
in each second type region, the first trench structure is a trench emitter structure and an emitter contact region surrounds the trench emitter structure.

### Claim 17

A power semiconductor device comprising:
a substrate comprising a drift region having a first conductivity type, an emitter contact region, a base region having a second conductivity type and located between the drift region and the emitter contact region, and an electrically floating region;
an emitter electrode located on a first surface of the substrate and in contact with the emitter contact region;
a drain electrode located on a second surface of the substrate that is opposite to the first surface;
a trench structure surrounding an enclosed region of the substrate using trench walls that extend from the first surface of the substrate toward the drift region,
wherein the electrically floating region is bounded by the trench walls and extends around an end surface of each trench wall to prevent contact of the end surfaces with the drift region.

### Claim 18 (depends on 17)

The power semiconductor device of claim 17, wherein
the trench structure comprises a trench gate structure and the emitter contact region is within the enclosed region.

### Claim 19 (depends on 17)

The power semiconductor device of claim 17, wherein
the trench structure comprises a trench emitter structure and the electrically floating region is within the enclosed region

### Claim 20 (depends on 17)

The power semiconductor device of claim 17, wherein
the substrate further comprises a termination region surrounding a cell region, the cell region comprises the trench structure and the floating region, and the termination region comprises a termination ring region and a gate bus line.