# US 2017/0256586 A1 · Semiconductor memory device

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- Number: US 2017/0256586 A1
- Document ID: US20170256586A1
- Status: Published application
- Kind: A1
- Application number: 15/074,395
- Filed: 2016-03-18
- Published: 2017-09-07
- Earliest claimed: 2016-03-04
- Assignees: Kabushiki Kaisha Toshiba
- Applicants: Kabushiki Kaisha Toshiba
- Inventors: Masato SHINI
- Web page: https://patentgrep.com/patent/US20170256586A1

## CPC

- H10B 63/845: {the switching components being connected to a common vertical conductor}
- H10B 63/22: {of the metal-insulator-metal type}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A semiconductor memory device according to an embodiment comprises: a first wiring line extending in a first direction; a second wiring line extending in a second direction, the second direction intersecting the first direction; and a memory cell disposed at an intersection of the first wiring line and the second wiring line, the memory cell including a first film whose resistance changes electrically, a second film having conductivity, and a third film having an insulating property which are stacked sequentially in a third direction that intersects the first and second directions.

## Claims

### Claim at position 1

-6. (canceled)

### Claim 7

A semiconductor memory device, comprising:
when three directions crossing each other are set to first, second, and third, directions, respectively,
a plurality of first wiring lines which are arranged in the third direction, and which extend in the first direction;
a second wiring line extending in the third direction;
a plurality of memory cells disposed at intersections of the plurality of first wiring lines and the second wiring line; and
a first insulating film disposed between two of the first wiring lines adjacent in the third direction,
one of the memory cells including a first film whose resistance changes electrically, a second film having conductivity, and a third film having an insulating property which are stacked sequentially in the second direction, and
the two first wiring lines being more distantly separated from the second wiring line in the second direction than the first insulating film.

### Claim 8 (depends on 7)

The semiconductor memory device according to claim 7, wherein a thickness in the second direction of the second film is larger than a thickness in at least one of the first direction and the third direction of the second film.

### Claim 9 (depends on 7)

The semiconductor memory device according to claim 7, wherein a thickness in the second direction of the second film is larger than a thickness in the second direction of the first film.

### Claim 10 (depends on 7)

The semiconductor memory device according to claim 7, wherein the first film includes hafnium oxide (HfO2).

### Claim 11 (depends on 7)

The semiconductor memory device according to claim 7, wherein the second film includes a metal.

### Claim 12 (depends on 7)

The semiconductor memory device according to claim 7, wherein the third film includes silicon oxide (SiO2).

### Claim 13 (depends on 7)

The semiconductor memory device according to claim 7, wherein the first film has a filament.

### Claim 14 (depends on 7)

The semiconductor memory device according to claim 7, wherein the first films of two of the memory cells adjacent in the third direction are integrated.

### Claim 15 (depends on 7)

The semiconductor memory device according to claim 7, wherein the second films of two of the memory cells adjacent in the third direction are separated between the two memory cells.

### Claim 16 (depends on 7)

The semiconductor memory device according to claim 7, wherein the third films of two of the memory cells adjacent in the third direction are integrated.

### Claim 17

(canceled)

### Claim 18 (depends on 7)

The semiconductor memory device according to claim 7, further comprising
two of first insulating films sandwiching one of the first wiring lines in the third direction,
wherein the third film contacts a side surface facing the second direction and upper surface of one of the two first insulating films, a side surface facing the second direction of the first wiring line, and a bottom surface and side surface facing the second direction of the other of the two first insulating films.

### Claim 19 (depends on 7)

The semiconductor memory device according to claim 7, wherein a side surface facing the second direction of the second film and a side surface facing the second direction of the third film are disposed in an identical plane.

### Claim 20 (depends on 7)

The semiconductor memory device according to claim 7,
wherein the first film contacts the third film at the same position in the third direction as the first insulating film.

### Claim 21 (depends on 7)

The semiconductor memory device according to claim 7, further comprising
a semiconductor substrate which extends in the first direction and the second direction.