# US 2017/0256567 A1 · Thin film transistor array panel

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- Number: US 2017/0256567 A1
- Document ID: US20170256567A1
- Status: Published application
- Kind: A1
- Application number: 15/602,018
- Filed: 2017-05-22
- Published: 2017-09-07
- Earliest claimed: 2014-02-17
- Assignees: Samsung Display Co., Ltd.
- Applicants: Samsung Display Co., Ltd.
- Inventors: Eun Hyun Kim
- Web page: https://patentgrep.com/patent/US20170256567A1

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- H10D 30/6729: {characterised by the electrodes}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A thin film transistor array panel includes: a substrate; gate lines on the substrate, each of the gate lines including a gate electrode; a semiconductor layer on the substrate; an etching stopper on the semiconductor layer; a data wiring layer on the substrate and including a data line, a source electrode connected to the data line, and a drain electrode; and a passivation layer covering the source electrode, the drain electrode, and the etching stopper, where the etching stopper includes an etching prevention portion between the source electrode and the drain electrode, a shortest distance A between an upper side and a lower side of an overlap area where the etching prevention portion and the semiconductor layer overlap one another is represented by a straight line in a plane view, and a width of a channel portion of the semiconductor layer is greater than the shortest distance A.

## Claims

### Claim 1

A thin film transistor array panel comprising:
a substrate;
gate lines on the substrate, each of the gate lines comprising a gate electrode;
a semiconductor layer on the substrate;
a gate insulating layer between the gate electrode and the semiconductor layer;
an etching stopper on the semiconductor layer;
a data wiring layer on the substrate, the data wiring layer comprising a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode; and
a passivation layer covering the source electrode, the drain electrode, and the etching stopper,
wherein the etching stopper comprises an etching prevention portion between the source electrode and the drain electrode,
a shortest distance A between an upper side and a lower side of an overlap area where the etching prevention portion and the semiconductor layer overlap one another is represented by a straight line in a plane view, and
a width of a channel portion of the semiconductor layer is greater than the shortest distance A, and
the etching stopper is an island on the semiconductor layer.

### Claim 2 (depends on 1)

The thin film transistor array panel of claim 1, wherein the etching stopper has a shape that is oblique with respect to the straight line that represents the shortest distance A.

### Claim 3 (depends on 2)

The thin film transistor array panel of claim 2, wherein the etching stopper comprises a bent portion.

### Claim 4 (depends on 1)

The thin film transistor array panel of claim 1, wherein the etching stopper comprises a bent portion.

### Claim 5 (depends on 4)

The thin film transistor array panel of claim 4, wherein one side of the etching stopper comprises a protrusion portion and an other side of the etching stopper comprises a recess portion and the one side and the other side of the etching stopper face each other.

### Claim 6 (depends on 5)

The thin film transistor array panel of claim 5, wherein the protrusion portion comprises a plurality of protrusions and the recess portion comprises a plurality of recesses.

### Claim 7 (depends on 5)

The thin film transistor array panel of claim 5, wherein each of the protrusion portion and the recess portion of the etching stopper is rounded.

### Claim 8 (depends on 1)

The thin film transistor array panel of claim 1, wherein an exposed portion of the semiconductor layer between the source electrode and the drain electrode and contacting the passivation layer has a shape of a straight line.

### Claim 9 (depends on 1)

The thin film transistor array panel of claim 1, wherein the source electrode and the drain electrode overlap lateral facing edges of the etching stopper.